# SoC Design Verification Engineer at Intel

Intel is hiring a SoC Design Verification Engineer in Santa Clara, United States. It pays $106k-$149k a year and Level rates it Little AI ●○○○; you can [apply on Intel](https://jobsbylevel.com/go/8f9302d1-283b-45fc-8f13-0956b77c4e43?utm_medium=ai-agent).

AI Level 1, AI centrality 31 out of 100. US, California, Santa Clara.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 31 out of 100)
- Location: US, California, Santa Clara
- Salary: $106k-$149k
- Posted: November 9, 2026
- Apply: https://jobsbylevel.com/go/8f9302d1-283b-45fc-8f13-0956b77c4e43?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=soc-design-verification-engineer-at-intel-e37ab5

## Description

Job Details: Job Description: The Role and Impact accuracy and functionality of Intel's next-generation Xeon server SoCs. Your day-to-day responsibilities will focus on performing functional logic verification, developing scalable verification plans, and executing emulation models to uncover and address design challenges. Your contributions will directly enhance the quality, reliability, and performance of Intel's flagship server products, making this position integral to delivering cutting-edge technology to global markets. You will be joining Intel's Data Center Group (DCG), a dynamic organization dedicated to advancing the capabilities of the world's data centers. DCG focuses on developing innovative server technologies that drive business transformation, cloud computing, and AI workloads. As part of this team, you will help propel Intel's vision of creating world-changing technology that enriches the lives of every person on earth. The primary responsibilities for this role will include, but are not limited to: Perform functional logic verification of integrated SoC designs to ensure adherence to specifications. Define and develop scalable and reusable block, subsystem, and SoC verification plans, test benches, and environments. Execute verification plans utilizing emulation and system simulation models to evaluate design power, performance, and functionality. Debug and analyze issues in the pre-silicon environment and implement corrective measures for resolution. Collaborate with architects, RTL developers, and post-silicon teams to improve verification processes for complex architectural features. Document technical test plans and participate in reviews with design and architecture teams. Incorporate security test coverage within the verification environment to ensure compliance with security requirements. Maintain and optimize existing functional verification methodologies for continuous improvement. Absorb post-silicon learnings to refine pre-silicon validation strategies for future projects. Qualifications: Minimum Qualifications : Minimum qualifications are required to be initially considered for this position. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 0-1 years of hands-on experience in silicon design and/or validation gained through internships, academic projects, coursework, or hands-on training OR Master's degree in the same fields with no prior professional experience required. Demonstrated coursework or technical experience in silicon design and/or validation/verification. Preferred Qualifications: Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience with developing and verifying complex IPs and/or SoCs using UVM/SystemVerilog. Knowledge of OVM/UVM, constrained random verification methodologies, and the complete verification lifecycle, including test plan development, execution, debug, and coverage closure. Proficiency in scripting languages for automation and process improvement. Familiarity with cache coherency principles and layered protocols in multi-processor SoCs. Experience with Xeon CPU pre-silicon, emulation validation, or post-silicon validation. Strong analytical, debugging, and problem-solving skills with a proactive mindset for task ownership and collaboration. We invite you to bring your skills and passion to Intel, where you'll have the opportunity to grow your expertise, innovate on impactful projects, and contribute to building a brighter future in technology. Job Type: College Grad Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information,

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/soc-design-verification-engineer-at-intel-e37ab5

Source: https://jobsbylevel.com/jobs/soc-design-verification-engineer-at-intel-e37ab5

## Cite this page

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