# Sr Director, XSE Design Verification Engineering Manager at Intel

Intel is hiring a Sr Director, XSE Design Verification Engineering Manager in Santa Clara, United States. It pays $256k-$361k a year and Level rates it Little AI ●○○○; you can [apply on Intel](https://jobsbylevel.com/go/2ea7bc80-95e9-48d2-8479-b803c13d6f37?utm_medium=ai-agent).

AI Level 1, AI centrality 35 out of 100. US, California, Santa Clara.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 35 out of 100)
- Location: US, California, Santa Clara
- Salary: $256k-$361k
- Posted: October 30, 2026
- Apply: https://jobsbylevel.com/go/2ea7bc80-95e9-48d2-8479-b803c13d6f37?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=sr-director-xse-design-verification-engineering-manager-at-intel-ccc14c

## Description

Job Details: Job Description: The Role and Impact As a Design Verification Engineering Manager, you will lead a dynamic team of design verification engineers responsible for Xeon SoC design verification. You will deploys and manage leading silicon design verification processes, procedures, verification tools, and technologies based on latest best industry practices. You will work with design, microarchitecture, and post-silicon validation teams to identify design bugs and improve overall microarchitecture. You will also bring a culture of rapid execution with high quality and simplify complicated process flows. This critical role ensures delivery excellence, directly contributing to Intel's broader success in creating innovative technology solutions. Business group The Data Center Group (DCG) is at the forefront of Intel's mission to deliver advanced technologies that power cloud computing, enterprise, AI, and edge solutions. Within DCG, the DSE Xeon SoC Engineering organization specializes in developing cutting-edge SoC designs to drive next-generation data center performance. Joining this team means being part of a collaborative environment dedicated to shaping the future of data-driven innovation. Key Responsibilities - Present status of Verification and quality of design to senior executives in clear and concise manner and present solutions when design hits critical issues. - Collaborates with program leaders on the verification delivery and regression metrics against milestone requirements. Understands security milestone expectations and works with SoC security validation teams to incorporate security-related testing through validation, hackathon reviews, and new validation techniques to improve security coverage. Executes security and security development lifecycle tasks per job role and schedule milestones. - Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results. - Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment. Create future technical leaders who imbibe the rapid execution and can-do attitude. Qualifications: Minimum Qualifications - Bachelor's, Master's, or PhD in Electrical Engineering, Computer Science, or a related field. - 12+ years of experience in ASIC/SoC design and verification with a Bachelor's degree, 8+ years with a Master's degree, or 6+ years with a PhD. - Comprehensive knowledge of industry-standard protocols. Preferred Qualifications - Proven experience in formal people management or leadership roles, with 5-10+ years in managing technical teams. - Familiarity with AI and GPU technologies. - Experience with hardware emulation platforms. - Strong interpersonal and communication skills to effectively lead cross-functional teams and drive results. We invite you to bring your leadership, technical expertise, and passion for innovation to Intel, where you'll have the opportunity to make a meaningful impact on groundbreaking technologies. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/sr-director-xse-design-verification-engineering-manager-at-intel-ccc14c

Source: https://jobsbylevel.com/jobs/sr-director-xse-design-verification-engineering-manager-at-intel-ccc14c

## Cite this page

Level. https://jobsbylevel.com/jobs/sr-director-xse-design-verification-engineering-manager-at-intel-ccc14c.

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