# Sr. Manager, Physical Design Engineering, Annapurna Labs at Amazon

Amazon is hiring a Sr. Manager, Physical Design Engineering, Annapurna Labs in Toronto, Canada. It pays CAD 208k-CAD 347k a year and Level rates it Little AI ●○○○; you can [apply on Amazon](https://jobsbylevel.com/go/f4e911fe-1e29-42ac-a579-f8e79b0a7286?utm_medium=ai-agent).

AI Level 1, AI centrality 30 out of 100. CA, ON, Toronto.

## Details

- Company: [Amazon](https://jobsbylevel.com/companies/amazon)
- AI level: AI Level 1 (score 30 out of 100)
- Location: CA, ON, Toronto
- Salary: CAD 208k-CAD 347k
- Posted: August 20, 2026
- Apply: https://jobsbylevel.com/go/f4e911fe-1e29-42ac-a579-f8e79b0a7286?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=sr-manager-physical-design-engineering-annapurna-labs-at-amazon-1c84c4

## Prepare for this job

The job page lists 5 likely interview questions for this offer, with a CV checklist: https://jobsbylevel.com/jobs/sr-manager-physical-design-engineering-annapurna-labs-at-amazon-1c84c4

## Description

Annapurna Labs, designs custom silicon powering AWS’s cloud infrastructure. Custom SoCs live at the heart of Amazon ML servers — including Inferentia and Trainium Systems — delivering high-performance ML inference and training at cloud scale. We’re looking for a Senior Manager, Physical Design Engineering to build and lead a world-class Physical Design team delivering multi-billion-transistor ML accelerator SoCs on latest tech nodes. This is a player-coach role: you will personally engage in the most critical technical decisions; chip-level floorplan architecture, multi-GHz timing convergence, high-speed I/O physical design, power delivery for KW class systems, and 2.5D / 3D integrations; while building a high-performing team and driving rigorous PPA targets, first-pass silicon success, and relentless continuous improvement. Key job responsibilities - Build, hire, and develop a physical design team of 10-15 engineers. Own headcount planning, performance management, career growth, and organizational scaling to support multiple concurrent tapeouts. - Own the physical design strategy and execution roadmap across Inferentia, Trainium, and future products: implementation architecture, hierarchical methodology, PPA target-setting, and technology node adoption. - Institutionalize continuous PPA improvement: benchmarking frameworks, regression tracking, design-quality dashboards, post-tapeout retrospectives, and structured improvement programs that compound across generations. - Provide hands-on technical leadership on the hardest problems: multi-GHz timing closure, PDN architecture, high-speed I/O physical design, and 2.5D / 3D cross-die integration. - Lead technology node enablement for 2nm and beyond: PDK evaluation, reference flow development, PPA pathfinding, and adoption recommendations. - Define and deploy innovative RTL2GDS methodologies and CAD flows. Champion AI/ML-augmented design automation (RL-placement, ML-guided ECO, predictive analytics). Optimize cloud infrastructure for PD compute. - Serve as part of senior technical interface with foundry partners and EDA vendors on tool roadmap, co-development, and technology co-optimization. - Own tapeout execution: readiness reviews, foundry submittal, mask data coordination, and post-silicon yield learning. Drive cross-functional alignment with RTL, DFT, STA, Package, and Validation teams. Basic qualifications - 5+ years people management leading PD teams of 8+ engineers, including hiring, performance management, and organizational growth. - 10+ years hands-on ASIC/SoC physical design across multiple advanced nodes (7nm, 5nm, 3nm) with multiple successful tapeouts. - Technical depth across full RTL-to-GDSII: floorplanning, CTS, routing, timing closure, PDN design, IR-drop/EM signoff, physical verification, and tapeout. - Mastery of both EDA ecosystems: Synopsys (Fusion Compiler/ICC2, PrimeTime, StarRC, RedHawk-SC) AND Cadence (Innovus, Tempus, Quantus, Voltus). Physical verification with Siemens Calibre (DRC, LVS, PERC). - Deep expertise in advanced STA (MMMC, POCV/AOCV, SSTA, PBA, IR-aware timing) and power integrity (static/dynamic IR-drop, EM, rush current, Ldi/dt, package-aware analysis). - Proven expertise in high-speed PD (multi-GHz datapaths, SerDes, DDR5, HBM, PCIe Gen5+, UCIe) and low-power design (UPF, power gating, DVFS, retention). - Experience with hierarchical methodologies for very large SoCs (>1B transistors). Expert scripting in TCL, Python, Perl. Preferred qualifications - Experience leading PD for AI/ML accelerators, GPUs, or high-performance data-center SoCs at leading semiconductor companies or hyperscalers. - Direct 3nm GAA/Nanosheet experience; 2nm or sub-2nm engagement. Familiarity with CFET and backside power delivery (BSPDN). - Quantifiable track record of continuous PPA improvement and metric-driven flow development across multiple projects and nodes. - Strong program execution: managing concurrent tapeouts, milestone tracking, risk identification,

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/sr-manager-physical-design-engineering-annapurna-labs-at-amazon-1c84c4

Source: https://jobsbylevel.com/jobs/sr-manager-physical-design-engineering-annapurna-labs-at-amazon-1c84c4

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