# Verification Engineer at Intel

Intel is hiring a Verification Engineer in Bengaluru, India. Level rates it Little AI ●○○○; you can [apply on Intel](https://jobsbylevel.com/go/2d76dde9-09b9-4836-88a9-d565a536c8e1?utm_medium=ai-agent).

AI Level 1, AI centrality 0 out of 100. India, Bangalore.

## Details

- Company: [Intel](https://jobsbylevel.com/companies/intel)
- AI level: AI Level 1 (score 0 out of 100)
- Location: India, Bangalore
- Posted: November 3, 2026
- Apply: https://jobsbylevel.com/go/2d76dde9-09b9-4836-88a9-d565a536c8e1?utm_medium=ai-agent
- Free CV review for this job: https://jobsbylevel.com/cv-review?job=verification-engineer-at-intel-13b329

## Prepare for this job

The job page lists 5 likely interview questions for this offer, with a CV checklist: https://jobsbylevel.com/jobs/verification-engineer-at-intel-13b329

## Description

Job Details: Job Description: Intel is seeking a highly qualified candidate to join our ASIC design verification team in a dynamic and forward-thinking organization focused on next-generation semiconductor product development. Our team focuses on being nimble, adaptable, lean and efficient to drive cutting-edge, customer impacting technology development. We embrace innovative and efficient methodologies that drive at-scale product execution. Advance your career with cutting-edge verification techniques including coverage-driven verification, formal methods, and performance analysis. Lead custom SystemVerilog/UVM development, master industry-standard EDA tools, architect verification strategies for complex ASICs, and mentor emerging talent while independently driving verification closure. Join our fast-paced semiconductor team where your technical leadership shapes next-generation chip development through comprehensive methodologies and innovative verification solutions. Transform challenging projects into career-defining achievements. If you are passionate about building products faster and more efficiently than anyone else on the planet, we want you on our team. Key Responsibilities: • Define Project Specific Verification Strategy: Defines and implement scalable and reusable verification plans, test benches, and the verification environments for blocks, subsystems, and SoCs. Ensure meeting the required coverage levels and confirm to microarchitecture specifications. • Lead Verification Execution: Create detailed test plans and drives technical reviews with design and architecture teams to validate these plans and proofs. • Executes verification plan: Implement and run block/subsystem/cluster/soc simulation models to verify the design, analyze power and performance, and identify bugs. • Investigate and Resolve Bugs: Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. • Collaborate Across Teams: Work closely with SoC architects, micro architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. • Enhance Future Verification Methodologies: Continuously improves existing functional verification infrastructure and methodologies. • Absorbs learnings: From post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages and proliferates to future products. • Lead and mentor others: inspire and guide junior engineers, fostering their growth and development. Your expertise will be instrumental in cultivating a collaborative and innovative environment where every team member thrives. Qualifications: Minimum Qualifications: You must possess the below minimum qualifications to be initially considered for this position. • Bachelor's degree in electrical engineering, computer engineering, computer science, or in other relevant STEM related degree. • 6+ years of experience in ASIC/FPGA design verification • Strong understanding of object-oriented programming (OOP) principles and their application in SystemVerilog UVM or other verification methodologies. • Developing UVM and/or Formal based verification architectures and methodologies. • Experience with industry standard protocols (AMBA AXI/AXI-S/CHI and Low-speed communication protocols (UART, SPI, I2C/I3C)) • Hands-on experience with simulators (Synopsys VCS, Cadence Xcelium, or equivalent). • Familiarity with coverage-driven verification, constrained-random testing and strong debugging skills. • Experience with scripting languages. Preferred Qualifications: • Graduate/post-graduate degree in electrical engineering, computer engineering, computer science, or any STEM related degree with overall 8+ yrs. of experience. • Skilled in various validation concepts and debug techniques relevant to ASIC/FPGA domain. • Collaborative, able to

The description is cut here. Read the full offer: https://jobsbylevel.com/jobs/verification-engineer-at-intel-13b329

Source: https://jobsbylevel.com/jobs/verification-engineer-at-intel-13b329

## Cite this page

Level. https://jobsbylevel.com/jobs/verification-engineer-at-intel-13b329.

Get job alerts: https://jobsbylevel.com/newsletter