Level

HP

ASIC Design Engineer

AI in this role

ASIC Design Engineer

Description -

Description

We are looking for a motivated ASIC Design Engineer to support the development of digital ASIC components for printing systems. The candidate will work closely with experienced engineers and contribute to design implementation, verification, and system integration activities.

Key Responsibilities:

  • Design and develop functional blocks and subsystems of digital ASICs from specification through RTL implementation, verification, silicon validation, and qualification.
  • Support silicon validation and debug activities under the guidance of senior engineers.
  • Collaborate with cross-functional teams to align on specifications, conduct design reviews, and maintain clear technical documentation
  • Contribute ideas to future ASIC design improvements and innovation efforts.
  • Develop understanding of Inkjet and LaserJet print architecture and data path requirements to support effective ASIC design and integration.
  • Support FPGA or software-based prototyping of ASIC designs to enable pre-silicon and post-silicon firmware development and system verification.
  • Contribute to design methodology improvements and tool automation to enhance engineering efficiency and design quality.

Individuals who do well in this role typically have:

  • BS or MS degree in Electrical Engineering, Computer Engineering, or a related field, with a focus on VLSI or digital design.
  • Minimum of 3 years of ASIC or SoC design experience.
  • Familiarity with the digital ASIC/SoC design flow from RTL development through silicon characterization.
  • Familiarity with Synopsys and Cadence EDA tools for simulation, synthesis, static timing analysis (STA), formal verification, and assertion-based verification.
  • Proficiency in Verilog/SystemVerilog and familiarity with scripting or programming languages such as Python, Perl, C, or C++.
  • Familiarity with version control and collaborative development workflows using tools such as Git or GitHub.
  • Strong analytical and problem-solving skills and willingness to learn
  • Good communication and teamwork skills
  • Working knowledge of electronic components, printed circuit assembly (PCA) design, and common lab test equipment is an advantage.

Experience in one or more of the following areas is a strong plus:

  • Basic knowledge of Inkjet or LaserJet printing technology
  • FPGA design methodology using Xilinx or Intel/Altera tools.
  • Design database management, scripting, and design flow automation.
  • ARM-based processor or subsystem design including AMBA/AXI/AHB/APB familiarity
  • Memory and storage subsystems such as DDR, Flash, and eMMC.
  • Use of AI tools and scripting to improve design, verification, debug, and automation efficiency.
  • General AI knowledge and practical use of AI tools for research, learning, documentation, and problem-solving.

#Li-Post

Job -

Engineering

Schedule -

Full time

Shift -

No shift premium (Singapore)

Travel -

25%

Relocation -

No

Equal Opportunity Employer (EEO) - 

HP, Inc. provides equal employment opportunity to all employees and prospective employees, without regard to race, color, religion, sex, national origin, ancestry, citizenship, sexual orientation, age, disability, or status as a protected veteran, marital status, familial status, physical or mental disability, medical condition, pregnancy, genetic predisposition or carrier status, uniformed service status, political affiliation or any other characteristic protected by applicable national, federal, state, and local law(s).

Please be assured that you will not be subject to any adverse treatment if you choose to disclose the information requested. This information is provided voluntarily. The information obtained will be kept in strict confidence.

For more information, review HP’s EEO Policy or read about your rights as an applicant under the law here: “Know Your Rights: Workplace Discrimination is Illegal"

How we rate this

ASIC Design Engineer at HP rates 17 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

  1. ●●●● Builds AI80 to 100
  2. ●●●○ Works on AI60 to 79
  3. ●●○○ Uses AI40 to 59
  4. ●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Open the description and count.

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