DFT Design Engineer
AI in this role
DFT design engineer responsible for scan architecture implementation, ATPG, memory BIST, and DFT verification.
Job Description:
- Strong knowledge and experience in Spyglass DFT, Scan Architecture (SSN Topology), ATPG and various fault models.
- Hands on skills to implement JTAG, Memory BIST and Memory Repair (BIRA/BISR) circuitry using industry standard tools.
- Hands on experience in DFT verification using Gate Level Simulations with timing annotations.
- Hands on experience in solving DFT problems, simulation failures, ATPG coverage improvements and DRC debug.
- Good understanding of timing constraints and DFT mode timing analysis.
- Proficiency in RTL coding, shell scripting.
- Experience working with post-Silicon/manufacturing teams on ATE, including debugging and resolving issues.
Qualifications:
B.E/B.Tech/M.E/M.Tech in Electrical/Electronics/Communication Engineering with 2+ years of DFT experience.
Job Type:
Intel Contract EmployeeShift:
Shift 1 (India)Primary Location:
India, BangaloreAdditional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust
N/AWork Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.How we score this
DFT Design Engineer at Intel scores 0 out of 100 on AI centrality, which makes it AI Level 1 of 4 (Little AI) on this board. The level measures how much of the work is AI, not seniority.
AI Level 1. The work itself involves no AI, or AI only appears as scenery, such as a company tagline.
- AI Level 480 to 100
- AI Level 360 to 79
- AI Level 240 to 59
- AI Level 10 to 39
Bands come from how often the tools, models and workflows of the role are named in the posting itself. Open the description and count.
Prepare for this job
A free preview built only from this posting: what it asks for, what you could be asked in an interview, and how to adjust your resume.
Skills and AI tools this role asks for
Questions you could be asked
- Tell me about a project where dft was part of your work. What did you do?
- Tell me about a project where rtl coding was part of your work. What did you do?
- Tell me about a project where shell scripting was part of your work. What did you do?
- Tell me about a project where gate level simulation was part of your work. What did you do?
- Walk me through how you've used Spyglass Dft in your day-to-day work.
Adapt your resume
- List these exact terms on your resume: Dft, Rtl Coding, Shell Scripting, Gate Level Simulation, and Spyglass Dft. An applicant tracking system matches the wording, not the idea.
- Attach one line of real, concrete experience to at least one of them — a tool named with nothing behind it rarely survives a human read.
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