Level

AmazonPosted 1w ago

L1

Junior Design Verification Engineer, Amazon Leo

Junior Design Verification Engineer, Amazon Leo at Amazon scores 20 out of 100 on AI centrality, which makes it a Level 1 role on this board.

US, TX, Austinjuniorfull-time$110k-$160k

AI in this role

Implement verification environments and test plans for satellite communication ASIC chips using UVM and AI-assisted tools.

verilogsystemveriloguvmmatlab
Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.

The Role:
Be part of Leo's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies.

In this role you will:
· Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models
· Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program
· Participate in the validation of ASIC implementations in Verilog/SystemVerilog
· Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM
· Develop a highly automated environment to run regressions that can be used to make builds and maintain organization of the database


Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.



Basic qualifications

- Bachelor's degree in Electrical / Communications Engineering or Computer Science, or related field, or equivalent experience
- 2+ years in verification preferably in communication systems
- 2+ years in UVM

Preferred qualifications

- Master's or Ph.D degree in Electrical / Communications Engineering
- 3+ years in digital verification, preferably in communication systems
- Familiarity with Matlab
- Modem design verification experience
- System C, C or Matlab model : development or DV integration experience
- Comfortable using AI-assisted tools to accelerate verification workflows (testbench generation, debug, coverage analysis).
- Familiarity with formal verification techniques
- Strong written and verbal skills

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.

Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.

The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.



USA, TX, Austin - 109,700.00 - 160,000.00 USD annually

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Skills and AI tools this role asks for

VerilogSystemverilogUvmMatlab

Questions you could be asked

  1. What's a project where you used Verilog hands-on?
  2. Walk me through how you've used Systemverilog in your day-to-day work.
  3. What are the limits of Uvm that you've run into, and how did you work around them?
  4. What's a project where you used Matlab hands-on?

Adapt your resume

  • List these exact terms on your resume: Verilog, Systemverilog, Uvm, and Matlab. An applicant tracking system matches the wording, not the idea.
  • Attach one line of real, concrete experience to at least one of them — a tool named with nothing behind it rarely survives a human read.

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