PMU ASIC Engineer - New College Graduate 2027

NVIDIA is hiring a PMU ASIC Engineer - New College Graduate 2027 in Shanghai, China. Level rates it ; you can apply on Level.

Level's read on this job

On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
The posting mentions Risc V, asic design and rtl among its tools and skills.
Level classes it as a junior role.
NVIDIA has 2,700+ other open roles on Level.
This posting went up within the past week.

AI in this role

Implement micro-architecture to RTL design for next-generation power management unit (PMU) ASICs.

risc-v

asic-designrtlmicro-architecturepower-management

As chip sizes continue to grow, power efficiency(token per watt/dollar) has become critical across all NVIDIA products - from data centers to automotive and personal computing. Our PMU IP, developed over the past 17 years, is essential in optimizing chip performance and efficiency in both idle and active scenarios. The PMU IP consists of a RISC-V core and custom-designed lower power/active power/thermal control logic. It collects and processes temperature, power, VR, and idle telemetries from the entire chip. It works with software on the RISC-V core to determine efficient operating points for different workloads on different chips. We are seeking an ASIC Engineer who can help RTL coding or even architecting the next generation PMU for datacenter, GeForce, Auto, PC, Networking chips, etc.

What you’ll be doing:

Implement the micro-architecture to RTL design.
Handling the general chip sign off checklist for every milestone
Involve into the discussion with the architecture member or even the SW member for the motivation

What we need to see:

BS / MS in electrical / Microelectronics/ Integrated Circuits engineering.
Strong communication skills and proficient oral English since this role require frequent communication with external teams mainly in USA and India.
Familiar with frontend ASIC design.

Ways to stand out from the crowd:

Experience on thermal management/active power/low power design. For example, NAFLL ADC, AVFS, DVFS, PG/RG/CG, etc.
Play similar role in other system-level control features if not power related.

How we rate this

PMU ASIC Engineer - New College Graduate 2027 at NVIDIA rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Open the description and count.

Key facts

PMU ASIC Engineer - New College Graduate 2027 is an open job at NVIDIA.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in China, Shanghai.
The job was posted on October 12, 2026.
Seniority: junior.
Applications are handled by NVIDIA. Apply on NVIDIA

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Asic DesignRtlMicro ArchitecturePower ManagementRisc V

Questions you could be asked

Tell me about a project where asic design was part of your work. What did you do?
Tell me about a project where rtl was part of your work. What did you do?
Tell me about a project where micro architecture was part of your work. What did you do?
Tell me about a project where power management was part of your work. What did you do?
Walk me through how you've used Risc V in your day-to-day work.

Adapt your resume

List these exact terms on your resume: Asic Design, Rtl, Micro Architecture, Power Management, and Risc V. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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