Silicon Packaging Design Engineer

AI in this role

Job Details:

Job Description:

Join our team as a Silicon Packaging Design Engineer in the Data Center Group, where you will play a pivotal role in crafting cutting-edge silicon packaging solutions that drive Intel's innovation and technological leadership. In this role, you will be engaged in the end-to-end development of substrate designs, from concept to tapeout, ensuring optimized performance and manufacturability. Collaborating closely with cross-functional teams, your contributions will directly impact product quality, cost efficiency, and time-to-market for Intel's next-generation technologies. This is an exciting opportunity to start your career in a collaborative environment that fosters learning and professional growth. Key Responsibilities - Drive the complete development of substrate designs, starting from initial concept through tapeout. - Perform physical layout and routing of package designs, ensuring adherence to design requirements. - Conduct substrate fit and routing studies to establish optimal tradeoffs between design, performance, and cost. - Collaborate with silicon and hardware teams to optimize silicon-package-board performance and pinout configurations. - Define and implement substrate design rules to meet product and manufacturing requirements. - Perform internal and external design reviews, analyze data, and resolve design rule violations (DRCs). - Integrate design documentation and collateral into the product lifecycle management system. - Continuously seek opportunities to improve package design for manufacturability (DFM) and quality assurance.

Qualifications:

Minimum Qualifications
- Diploma in Electronic/ Electrical Engineering or a related field.
- six months or more years of work experience in Semiconductor field related to design of silicon packaging or PCB.
- Novice to intermediate proficiency in substrate design and development, including physical layout and routing.
- Basic understanding of I/O fundamentals, package interconnect, and power delivery principles.
- Familiarity with design for manufacturability (DFM) and quality assurance processes.
- Strong problem-solving skills with a disciplined approach to execution.

Preferred Qualifications

-Preferred experience into E-CAD tool.
- Effective communication skills to convey technical information and collaborate with cross-functional teams.
- A proactive mindset to identify design improvement opportunities and ensure alignment with project goals.
- Passion for driving innovation and contributing to complex engineering challenges.
This is your opportunity to be part of Intel's legacy of innovation while developing your skills and advancing your career. Apply now and help us shape the future of technology.

Job Type:

College Grad

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

Silicon Packaging Design Engineer at Intel rates 31 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.