ASIC Verification Lead

About Bull

Bull is a story. One with a century of European innovation and a working environment where experts design powerful, sustainable, and sovereign digital solutions, enabling states and industries to retain full control over their data and their AI.

Bull is also thousands of engineers, researchers and passionate tech people shaping the future of high‑performance computing, AI, and quantum technologies.

Every day, our teams push the boundaries of what is technologically possible – from next‑generation HPC architectures to exascale supercomputers – supported by world‑class R&D, more than 1,600 patents, and unique end‑to‑end capabilities spanning hardware design, software engineering, data science and quantum research.

We are a people‑centric, innovation‑driven company, where collaboration spans Europe, the Americas and India. We share a common vision of a responsible and sustainable innovation that delivers concrete impact for our customers.

We are searching for an Asic Verification Lead to join Bull's dynamic team.

In this role, you will play a key part in verifying complex ASIC architectures used in Bull’s high‑end and exascale servers. You will drive verification strategy, lead UVM‑based methodologies, and work closely with architecture and design teams to ensure the reliability and performance of advanced semiconductor designs.

Responsibilities:

• Acquire knowledge of the architecture and microarchitecture of the ASIC by studying specifications and interacting with the architecture and logical design teams.

• Participate in defining overall verification strategies and methodologies, and the required simulation environments. Develop, maintain and publish verification specifications.

• Write and perform closely test plans with the logical design team.

• Develop coverage models and verification environments using UVM-SystemVerilog / C ++

• Monitor, analyze and debug simulation errors.

• Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time.

• Submit recommendations on tools and methodologies to develop to improve productivity.

• Mentor junior engineers on how to produce a maintainable and reusable code across projects.

What we're looking for:

Education:

• Experience: 8+ years

• Education: Bachelor's Degree (BE / BTech) or Master's Degree (ME / MTech)

Competences & Skills:

• Integrating ASIC functional verification team.

• ASIC developed include network controller, router and cache coherence controller targeting Bull high-end servers and Bull high-performance ("big data" and "exascale" servers).

• Using “Constraint-Random, Coverage Driven” functional verification methodologies underlying UVM verification framework to ensure full and effective verification of complex ASIC.

• Participated in the successful verification of a complex SoC or ASIC.

• Mastering UVM or equivalent verification methodology.

Location: Madrid or Barcelona. Candidates from other locations in Spain may also be considered.

Benefits:

• Flexible Work Schedule: Half day Fridays and an intensive summer workday supporting work life balance.

• Learning and Growth: Opportunities to work with advanced AI technologies in an innovative and supportive R&D environment.

#Bull

Join us!

Here, your ideas, your curiosity and your technical excellence directly shape the next era of advanced computing - unlocking enterprise value, accelerating scientific progress and driving positive impact for society.