AI GPU Cache Designer

AI in this role

SoC Cache Design Engineer driving microarchitecture and RTL for Intel's AI hardware accelerators and processors.

verilogsystemverilog

rtl-designsoccache-designhardware-architecture

Job Details:

Job Description:

The Role and Impact As a SoC Cache Design Engineer, you will play a pivotal role in developing cutting-edge Cache subsystem design for Intel's AI SoCs. You will drive the micro architecture, register transfer level (RTL) coding, subsystem integration, and simulation processes to deliver high-quality, fully verified Cache that meet power, performance, and area targets. Your work will directly contribute to Intel's groundbreaking AI hardware solutions, ensuring they meet the rigorous demands of modern applications. Business group Intel's AI SoC organization is at the forefront of developing innovative products that power AI applications across diverse domains. From edge devices to data center accelerators, our team focuses on delivering high-performance, efficient, and scalable hardware solutions. As part of this group, you will collaborate with world-class engineers to advance Intel's leadership in AI hardware development and help shape the future of intelligent computing. Key Responsibilities - Evaluate architectural trade-offs to align design features with performance targets, power constraints, and system limitations. - Define and document microarchitecture specifications for complex SoC IP blocks, implement RTL in Verilog/SystemVerilog, and deliver synthesis- and timing-clean designs. - Collaborate closely with verification teams to ensure comprehensive validation and coverage of all design aspects. - Develop and maintain timing constraints for IP blocks, supporting physical design teams in synthesis, timing closure, and formal equivalence checks. - Lead silicon bring-up efforts, including post-silicon validation, debug, and performance analysis. - Mentor junior engineers and contribute to advancing best practices for design methodology and quality assurance.

Qualifications:

Minimum Qualifications - Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 12+ years of experience in RTL design for ASIC/SoC development; OR Master's degree in relevant field with 8+ years of experience; OR PhD in relevant field with 6+ years of experience. - Advanced proficiency in RTL design using Verilog/SystemVerilog and hands-on experience in SoC system integration. - Expertise in standard bus protocols (AXI, AHB) and embedded processor architectures. - Demonstrated ability to address design challenges, including clock domain crossings, power optimization, and timing closure. - Proficiency in scripting languages (e.g., Python, TCL) for automation and design flow customization. Preferred Qualifications - Strong knowledge of high-speed and low-power design techniques. - Familiarity with industry-standard EDA tools such as HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools (Xilinx Vivado, Altera Quartus II). - Experience in SoC multicore CPU subsystem design and GPU cache development. - Collaborative mindset and leadership skills, with a passion for innovation and solving complex technical challenges. Join us to shape the next generation of AI hardware and make an impact on tomorrow's technological advancements.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Santa Clara

Additional Locations:

US, California, Folsom, US, Oregon, Hillsboro, US, Texas, Austin

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

AI GPU Cache Designer at Intel rates 90 out of 100 for how much of the daily work is AI. That makes it Builds AI (AI Level 4 of 4). The level is about AI in the job, not seniority.

Classification

Builds AI. The job is building AI systems.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Open the description and count.

Prepare for this job

A free preview built only from this posting: what it asks for, what you could be asked in an interview, and how to adjust your resume.

Skills and AI tools this role asks for

Rtl DesignSocCache DesignHardware ArchitectureVerilogSystemverilog

Questions you could be asked

Tell me about a project where rtl design was part of your work. What did you do?
Tell me about a project where soc was part of your work. What did you do?
Tell me about a project where cache design was part of your work. What did you do?
Tell me about a project where hardware architecture was part of your work. What did you do?
Walk me through how you've used Verilog in your day-to-day work.

Adapt your resume

List these exact terms on your resume: Rtl Design, Soc, Cache Design, Hardware Architecture, and Verilog. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them — a tool named with nothing behind it rarely survives a human read.
Lead with what you built, trained or shipped — this role is judged on the AI system itself, not the tools around it.

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