ASIC Design Engineer, Clocks

NVIDIA is hiring an ASIC Design Engineer, Clocks in Shanghai, China. Level rates it ; you can apply on NVIDIA.

Level's read on this job

Little AI ●○○○ is how Level rates this role: aI is not part of the work.
The posting mentions Verilog, Perl and Python among its tools and skills.
Level classes it as a senior role.
NVIDIA has 2,700+ other open roles on Level.

AI in this role

Senior ASIC Design Engineer focused on GPU clock architecture, RTL design, and verification supporting graphics and AI hardware.

VerilogPerlPython

rtl-designasic-designlogic-synthesisverification

The NVIDIA GPU clocks group is looking for an excellent Senior ASIC Design Engineer to join the team. The Team is responsible for crafting all aspects of GPU clocking. We collaborate with the frontend design team to understand the clocking requirements for the chip, and work with backend teams to understand the physical restrictions. The GPU clocks group architects, designs and validates the clocks RTL. The complexity of clocks RTL has increased many fold to support our features that power our product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

What you’ll be doing:

As a Clocks team member, you will collaborate with other architects, ASIC designers and verification engineers to design high frequency and low power clocks. You should be able to engage with multiple teams and design the GPU clocks to satisfy all the architectural constraints. You will need to run and enhance some in-house flow to guarantee the good quality of clocks RTL and netlist, drive the issues to close. Together with other team members, we deliver clock information to SOC verification team, timing and DFT teams. You will use Perl/Python to improve the productivity of the above teams. Collaborate with software and silicon solution team to debug GPU clock silicon bugs in our new products.

What we need to see:

BS or (MS preferred) in EE or equivalent experience. 2+ years of meaningful work experience.
Your ability to thrive in a dynamically changing environment.
Validated experience in RTL design (Verilog), verification and logic synthesis. Your strong coding skills in Perl or Python or other industry-standard scripting languages.
Deep understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus. Good understanding of backend flows and requirements is a plus.
DFT knowledge is a plus. Experience in implementing on-chip clocking networks is desirable.
Excellent analytical and problem-solving skills. Fluent English (both written and spoken) and excellent communication skills.
Good team work spirit, easy to cooperate with team members.

How we rate this

ASIC Design Engineer, Clocks at NVIDIA rates 20 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

ASIC Design Engineer, Clocks is an open job at NVIDIA.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in China, Shanghai.
The job was posted on August 3, 2026.
Seniority: senior.
Applications are handled by NVIDIA. Apply on NVIDIA

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Rtl DesignAsic DesignLogic SynthesisVerificationVerilogPerlPython

Questions you could be asked

Tell me about a project where rtl design was part of your work. What did you do?
Tell me about a project where asic design was part of your work. What did you do?
Tell me about a project where logic synthesis was part of your work. What did you do?
Tell me about a project where verification was part of your work. What did you do?
Walk me through how you've used Verilog in your day-to-day work.

Adapt your resume

List these exact terms on your resume: Rtl Design, Asic Design, Logic Synthesis, Verification, and Verilog. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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