ASIC Design Engineer, High Speed IO

NVIDIA is hiring an ASIC Design Engineer, High Speed IO in Bengaluru, India. Level rates it ; you can apply on NVIDIA.

Level's read on this job

On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
Tools and skills the posting cites include Claude, Cursor and rtl design.
Level classifies it as a mid-level role.
Level lists 2,700+ other open roles at NVIDIA.
The role was posted within the past week.

AI in this role

Design and verify high-speed IO IPs for automotive chips using standard digital design techniques with minor optional AI tool usage.

ClaudeCursor

rtl-designasicdigital-designverilogsystem-verilog

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

We are now looking for RTL Design engineers for our High Speed IO IP's deployed in Automotive chips. As one of the primary designers, you will be responsible for UFS/Ethernet/PCIE/USB IP's of next generation chips. One should possess strong digital design and verification fundamentals.

What you'll be doing:

As a designer, be responsible for understanding the specific protocol concepts and features, make architectural trade-offs based on feature/performance/power requirements, analyze system implications, come up with the micro-architecture, implement RTL, drive the verification, close timing, and support silicon validation.

During the course of a project you would end up driving the following aspects of design for your unit:

Own micro-architecture and RTL development of design modules
Micro-architect features to meet performance, power and area requirements
Work with HW architects to define critical features
Partner with verification teams to verify the correctness of implemented features
Collaborate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.

What we need to see:

You should be BTech/MTech in EE, ECE or similar stream, having a proven track record with 2+ years of experience in crafting complex Units and CPU/micro-controller based Sub-systems
Knowledge of HSIO standards, protocols and architectures of modern SOC's would be a significant plus
Excellent influencing skills resulting in collaboration with cross-cultural, multi geography and matrixed teams
Good debugging, analytical and problem solving skills
Great interpersonal skills and ability to work as an excellent teammate
Working exposure with AI tools like Claude and Cursor would be a plus

We have some of the most brilliant and talented people in the world working for us. If you're creative and independent, with a genuine real passion for technology and improving the state of art, we want to hear from you!

Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/

#LI-Hydrid

How we rate this

ASIC Design Engineer, High Speed IO at NVIDIA rates 20 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

ASIC Design Engineer, High Speed IO is an open job at NVIDIA.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in India, Bengaluru.
The job was posted on November 2, 2026.
Seniority: mid.
Applications are handled by NVIDIA. Apply on NVIDIA

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Rtl DesignAsicDigital DesignVerilogSystem VerilogClaudeCursor

Questions you could be asked

Tell me about a project where rtl design was part of your work. What did you do?
Tell me about a project where asic was part of your work. What did you do?
Tell me about a project where digital design was part of your work. What did you do?
Tell me about a project where verilog was part of your work. What did you do?
Tell me about a project where system verilog was part of your work. What did you do?

Adapt your resume

List these exact terms on your resume: Rtl Design, Asic, Digital Design, Verilog, and System Verilog. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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