ASIC Design Verification Engineer - Slingshot
Hewlett Packard Enterprise is hiring an ASIC Design Verification Engineer - Slingshot. Level rates it ; you can apply on Hewlett Packard Enterprise.
Level's read on this job
- Little AI ●○○○ is how Level rates this role: aI is not part of the work.
- Level classifies it as a senior role.
- Level lists 1,700+ other open roles at Hewlett Packard Enterprise.
- The role was posted in the last few days.
AI in this role
This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office.
Who We Are:
Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.
Job Description:
About the Team and the Project
Our team develops HPE Slingshot, an industry-leading interconnect used in some of the world's largest HPC and AI systems (HPE Slingshot interconnect). As a Design Verification Engineer, you will work alongside experienced architects, logic designers, and verification engineers on the switch and NIC ASICs for a future generation of Slingshot. You will own the verification of blocks from test plan through sign-off, grow your technical depth with support from senior engineers, and help put emerging agentic AI workflows to work on complex engineering problems.
We are looking for engineers who want to work at the leading edge of high-performance interconnects for HPC and AI, who take ownership of their work, and who want to grow beyond a narrowly defined test-writing role.
Job Description
In this role you will be responsible for all phases of pre-silicon design verification, including design verification methodology, test-plan development, testbench development, coverage closure, and sign-off reviews.
Responsibilities
- Follow and improve the team's design verification methodology.
- Develop SystemVerilog and UVM testbench components, including bus functional models that drive and monitor stimulus.
- Plan and implement block level scoreboards and checkers to verify functional behavior.
- Write and analyze functional coverage to find verification gaps and drive coverage closure.
- Triage regression failures and identify logic bugs, while driving bug closure.
- Apply scripting, automation, and AI-assisted and agentic tools to improve the speed and quality of the verification process.
- Work with designers, architects, and project leads on design status, verification progress, and issue resolution.
- Work independently as a member of a project team that includes other VLSI engineers and internal and outsourced development partners.
- Provide guidance and mentoring to less experienced staff members.
Education and Experience Required
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
- 5+ years of experience in VLSI design, verification, or implementation.
Knowledge and Skills
- Strong knowledge of SystemVerilog and of OVM or UVM methodologies.
- Strong knowledge of programming and scripting languages, hardware description languages, and electronic design automation (EDA) tools.
- Strong analytical and problem solving skills.
- Ability to be self-directed in a distributed team environment.
- Strong written and verbal communication skills; mastery in English.
Preferred Skills
- Experience verifying high-speed networking, switching, or NIC ASICs.
- Experience with agentic AI coding tools and workflows applied to verification.
- Experience with Python, Perl, Tcl, or another scripting language in Linux development environments.
- Experience working as part of a geographically distributed team.
Accessibility
HPE is committed to creating an inclusive and accessible workplace and encourages applications from all qualified individuals, including those with disabilities. If you believe you require accommodation during any stage of the application or interview process, please submit your request by completing our secure form linked here.
Note: This option is reserved for applicants needing assistance/reasonable accommodation related to a disability.
What We Can Offer You:
Health & Wellbeing
We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
Personal & Professional Development
We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.
Unconditional Inclusion
We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.
Let's Stay Connected:
Follow @HPECareers on Instagram to see the latest on people, culture and tech at HPE.
#unitedstates#highperformancecomputeJob:
EngineeringJob Level:
TCP_03"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
– United States of America: Annual Salary USD 115,000 - 218,000 in Colorado // 109,000 - 251,000 in Minnesota & Wisconsin
The listed salary range reflects base salary. Variable incentives may also be offered."
Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html
The estimated job application period closure is February 1 2027; this timeline is provided for transparency and internal planning purposes.HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: Equal Employment Opportunity.
Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.
HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.
Recruitment Fraud Alert
We have become aware of an increase in fraudulent recruitment activities in which individuals impersonate our company or authorized recruitment agencies to offer fake employment opportunities. These scams may occur through false websites, emails, social media, or chat-based applications and often aim to obtain personal information or money. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We also never request personal information such as back account details, Social Security numbers, or national IDs via social media or chat applications.
All legitimate job opportunities will come through official company channels, and candidates are responsible for verifying the credentials of any third party claiming to represent the company. Any reliance on fraudulent communication is at the individual’s own risk, and HPE disclaims legal liability for any resulting damages. If you suspect recruitment fraud, do not share personal information or make any payments and report the incident to your local authorities immediately.
How we rate this
ASIC Design Verification Engineer - Slingshot at Hewlett Packard Enterprise rates 27 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.
Little AI. AI is not part of the work.
- ●●●● Builds AI80 to 100
- ●●●○ Works on AI60 to 79
- ●●○○ Uses AI40 to 59
- ●○○○ Little AI0 to 39
Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.
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