ASIC Engineering Technical Leader
Cisco is hiring an ASIC Engineering Technical Leader. Level rates it ; you can apply on Cisco.
Level's read on this job
- Level rates this role Builds AI ●●●●: the job is building AI systems.
- The posting mentions Cadence Virtuoso, Veriloga and Tcl among its tools and skills.
- Level classes it as a lead role.
- Cisco has 1,400+ other open roles on Level.
- Posted within the past week.
AI in this role
Define, design, and verify high-performance ASIC subsystems and mixed-signal architectures powering AI and cloud infrastructure.
Cisco is seeking an ASIC Engineering Technical Leader to join our world-class Silicon One Analog Circuit Design team in Thalwil, Switzerland, pioneering industry-leading high-speed mixed-signal architectures that power the AI and cloud infrastructure era.
Meet the Team
The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
Your Impact
As an ASIC Engineering Technical Leader, you will define, design, and verify high-performance ASIC subsystems deployed across a range of Cisco platforms. You will oversee the architecture and design of complex analog and mixed-signal circuits, driving innovative solutions and establishing robust verification strategies. By collaborating with cross-functional teams, you will influence packaging and hardware requirements to ensure all power, performance, and area goals are met. Your technical expertise will guide the development of reusable code methodologies, physical design functions, and advanced digital design flows, ultimately shaping the future of our high-volume ASIC releases.
Minimum Qualifications
- Masters + 8 years of related experience, or PhD + 5 years of related experience, or equivalent related work experience
- Extensive experience in high-frequency CMOS circuit design and custom analog and mixed-signal circuit design.
- Proficiency with the Cadence Virtuoso CAD design environment, including custom layout, DRC, LVS, and parasitic extraction.
- Strong programming skills utilizing languages such as Skill, VerilogA, Tcl, Perl, Python, Matlab, or C.
Preferred Qualifications
- Experience in high-speed wireline SerDes design, signal processing, and communication systems.
- Familiarity with digital design flow (synthesis and P&R) and additional CAD tools (Siemens/Mentor, Synopsys).
- Experience with coil design using EM field simulators (EMX, Momentum, HFSS) and knowledge of packaging technology.
- Hands-on experience with measurement equipment and in-depth knowledge of version and project management tools (e.g., SOS, Jira).
- A strong portfolio of publications and patents, with a proven ability to collaborate effectively within a multi-disciplined engineering team.
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
How we rate this
ASIC Engineering Technical Leader at Cisco rates 80 out of 100 for how much of the daily work is AI. That makes it Builds AI (AI Level 4 of 4). The level is about AI in the job, not seniority.
Builds AI. The job is building AI systems.
- ●●●● Builds AI80 to 100
- ●●●○ Works on AI60 to 79
- ●●○○ Uses AI40 to 59
- ●○○○ Little AI0 to 39
Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.
Prepare for this job
Built from this posting and from similar jobs on Level.
Skills and AI tools this role asks for
Questions you could be asked
- Tell me about a project where asic design was part of your work. What did you do?
- Tell me about a project where analog circuit design was part of your work. What did you do?
- Tell me about a project where mixed signal was part of your work. What did you do?
- Tell me about a project where hardware architecture was part of your work. What did you do?
- Walk me through how you've used Cadence Virtuoso in your day-to-day work.
Adapt your resume
- List these exact terms on your resume: Asic Design, Analog Circuit Design, Mixed Signal, Hardware Architecture, and Cadence Virtuoso. An applicant tracking system matches the wording, not the idea.
- Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.
- Lead with what you built, trained or shipped. This role is judged on the AI system itself, not the tools around it.
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