ASIC Physical Design Engineer
Cisco is hiring an ASIC Physical Design Engineer. Level rates it ; you can apply on Cisco.
Level's read on this job
- Level rates this role Little AI ●○○○: aI is not part of the work.
- Tools and skills the posting cites include Synopsys, Cadence and Python.
- Level classifies it as a senior role.
- Level lists 1,500+ other open roles at Cisco.
- The role was posted within the past two weeks.
AI in this role
Lead macro-level RTL-to-GDSII physical implementation and signoff for custom hardware platforms powering network infrastructure.
This is a hybrid role with four days per week at Cisco’s Yerevan office.
Meet the Team
The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
Your Impact
Lead macro-level RTL-to-GDSII physical implementation and signoff. Collaborate with Front-End teams to translate architecture into optimal physical design. Perform synthesis, floorplanning, placement, Clock Tree Synthesis, and routing. Optimize power, performance, and area while maintaining design correctness through formal verification. Execute static timing analysis, physical verification, formal checks, and signoff closure to ensure reliable, high-quality silicon. Analyze and resolve Electromigration and IR-drop issues to meet reliability and performance signoff targets.
Minimum Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.
- 5+ years of hands-on experience in ASIC design and physical implementation.
- Proven track record in ASIC physical design and verification preferably in complex SoC or block-level projects.
- Deep knowledge of block-level synthesis, place-and-route (PnR), and timing closure.
- Experience with industry-standard PnR and signoff tools (e.g., Synopsys, Cadence).
Preferred Qualifications
- Broad understanding of physical design methodologies, integration, and implementation flows.
- Experience in physical verification (LVS, DRC) and signoff processes.
- Familiarity with physical design EDA toolchains and end-to-end workflows.
- Advanced expertise in STA, timing closure, and constraint management.
- Proficiency in scripting (Tcl, Python, or Perl) for automation and productivity improvements.
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
How we rate this
ASIC Physical Design Engineer at Cisco rates 10 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.
Little AI. AI is not part of the work.
- ●●●● Builds AI80 to 100
- ●●●○ Works on AI60 to 79
- ●●○○ Uses AI40 to 59
- ●○○○ Little AI0 to 39
Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.
Prepare for this job
Built from this posting and from similar jobs on Level.
Skills and AI tools this role asks for
Questions you could be asked
- Tell me about a project where asic was part of your work. What did you do?
- Tell me about a project where physical design was part of your work. What did you do?
- Tell me about a project where rtl to gdsii was part of your work. What did you do?
- Tell me about a project where static timing analysis was part of your work. What did you do?
- Walk me through how you've used Synopsys in your day-to-day work.
Adapt your resume
- List these exact terms on your resume: Asic, Physical Design, Rtl To Gdsii, Static Timing Analysis, and Synopsys. An applicant tracking system matches the wording, not the idea.
- Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.
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