ASIC Physical Design Engineer

NVIDIA is hiring an ASIC Physical Design Engineer in Shanghai, China. Level rates it ; you can apply on NVIDIA.

Level's read on this job

On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
Tools and skills the posting cites include Python, Perl and Tcl.
Level classifies it as a junior role.
Level lists 2,700+ other open roles at NVIDIA.

AI in this role

Perform physical design and timing closure for advanced ASICs from RTL to GDSII using standard EDA tools and scripting languages.

pythonperltclsynopsyscadence

asic-designphysical-designtiming-closurestartl

ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also all related flow. Join us, you will work together with expertise in all these areas; you will not only work for physical application, but also drive physical friendly design with all related teams: ASIC/P&R/DFT/SI/ARCH etc.; you will work for the most advanced process/technology, the biggest chip in the world.

What you'll be doing:

STA for hierarchical design.
Constraints creation and validation, timing budget.
Timing closure for both partition and full chip level.
Special timing closure, such as io, test, clock etc.
Synthesis, Netlist quality check, Formal Verification.
Implement chip partition and floorplan.
Function eco creation.
Develop and enhance entire timing closure flow from frontend (pre-layout) to backend (post-layout).
Flow automation development, Methodology in any of above areas.

What we need to see:

MS in EE, CS or Microelectronics with 1+ year experience is preferred
Project experience in IC design implementation.
Courses taken in circuit design, digital design
Hand-on experience in EDA software from Synopsys (FC/DC/PT/Formality), Cadence (RC compiler/Genus/LEC) is helpful
Proficient user of Python, perl or TCL is helpful
Proficient in English reading and writing

Ways to stand out from the crowd:

Proficient user of Perl, Python or TCL is preferred.
Excellent English communication skill.

How we rate this

ASIC Physical Design Engineer at NVIDIA rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

ASIC Physical Design Engineer is an open job at NVIDIA.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in China, Shanghai.
The job was posted on October 5, 2026.
Seniority: junior.
Applications are handled by NVIDIA. Apply on NVIDIA

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Asic DesignPhysical DesignTiming ClosureStaRtlPythonPerlTcl

Questions you could be asked

Tell me about a project where asic design was part of your work. What did you do?
Tell me about a project where physical design was part of your work. What did you do?
Tell me about a project where timing closure was part of your work. What did you do?
Tell me about a project where sta was part of your work. What did you do?
Tell me about a project where rtl was part of your work. What did you do?

Adapt your resume

List these exact terms on your resume: Asic Design, Physical Design, Timing Closure, Sta, and Rtl. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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