Atom CPU Layout Design Engineer

Intel is hiring an Atom CPU Layout Design Engineer in Guadalajara, Mexico. Level rates it ; you can apply on Intel.

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The role was posted in the last few days.

AI in this role

Job Details:

Job Description:

The Role and Impact

As a Layout Design Engineer, you will play a critical role in the physical implementation of next-generation high-performance Intel Atom microprocessors. Your day-to-day responsibilities will include driving the design of memory compilers, custom IPs, and partitions that support CPU products. Your contributions will directly impact the efficiency and performance of Intel's cutting-edge technologies used globally.

Business Group

You will join Intel Corporation's ATOM GDC Physical Design organization, which focuses on delivering innovative and efficient physical design solutions for Intel Atom microprocessors. This group supports Intel's broader mission to create world-class semiconductor products that empower cutting-edge computing technologies.

Responsibilities will include but are not limited to

Perform and drive complex physical design assignments independently, ensuring best practices and high efficiency.
Collaborate closely with circuit design engineers to interpret schematics and enable successful physical implementation.
Lead physical design efforts ranging from leaf-level cell design to full partition integration.
Assess and implement solutions for custom IPs and memory compilers to support high-performance CPU products.
Develop and optimize layout scripts, macros, and tools to enhance design implementation workflows.
Work collaboratively with cross-functional teams across various Intel sites to align on design objectives.

The ideal candidate should show the following behavioral traits:

Good English communication skills.

Qualifications:

Minimum qualifications are required to be initially considered for this position.

Bachelor's degree in Electronics, Microelectronics Engineering, Computer Engineering, or a related engineering discipline.

6+ months of hands-on experience in:

- Layout design (experienced would be obtained through a combination, of relevant industry job experience, internship experience and/or schoolwork/classes/research).
- Industry-standard layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or similar software.

Advanced English level.

Must have unrestricted, permanent right to work in Mexico (this role is not eligible for visa or immigration sponsorship).

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Master's degree in Electronics, Microelectronics Engineering, Computer Engineering, or a related engineering discipline.
1+ years of experience or familiarity with Very Large-Scale Integration (VLSI) or Complementary Metal-Oxide-Semiconductor (CMOS) logic circuit design.
Practical knowledge of Unix/Linux operating systems.

Requirements listed would be obtained through a combination of relevant industry job experience, internship experience and/or schoolwork/classes/research.

We invite you to bring your creativity and technical expertise to Intel, where you'll contribute to shaping the future of computing technologies.

Your journey starts applying today and be part of Intel's innovation legacy.

Job Type:

Experienced Hire

Shift:

Shift 1 (Mexico)

Primary Location:

Mexico, Guadalajara

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

Atom CPU Layout Design Engineer at Intel rates 35 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.