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Intel

CPU HVM Functional-Test Verification Engineer

Intel is hiring a CPU HVM Functional-Test Verification Engineer. Level rates it ; you can apply on Intel.

Level's read on this job

  • Level rates this role Little AI ●○○○: aI is not part of the work.
  • Tools and skills the posting cites include Python, Perl and System Verilog.
  • Level classifies it as a mid-level role.
  • Level lists 805 other open roles at Intel.

AI in this role

Validates DFT for manufacturing functional testing and develops functional tests for next-generation CPU IP designs at Intel.

pythonperlsystem-veriloguvm
dftverificationdebuggingcpu-architecture
Job Details:

Job Description: 

As a CPU HVM Functional-Test Verification Engineer, you will be part of the DFT team focusing on validating DFT for manufacturing functional testing and delivering functional test content for the manufacturing of Intel's next generation CPU IP designs. Besides being part of DFT verification team, you will also have the opportunity to work in close partnership with CPU design/architecture, SOC design and manufacturing teams. Job scopes for this position are as follow:

  • Validates DFT for manufacturing functional testing
  • Develops functional tests to qualify manufacturing goals of next generation Intel CPU IP designs
  • Uses fault-simulator to measure coverage effectiveness of functional tests / understand and patch test gaps accordingly before high volume manufacturing
  • Replicates, root causes, and debugs test or design issues in pre-silicon environment.
  • Finds and implements corrective measures to resolve failing tests.

Qualifications:

Minimum Qualifications :

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • 2+ years of experience with a Bachelor's degree / Master's degree, or PhD.
  • Strong scripting and programming skills in languages, particularly Python, Perl and C/C++.
  • Robust understanding of CPU architecture and microarchitecture fundamentals.
  • Proficiency in System Verilog and UVM, and with experience debugging on any micro-architecture issue in pre-silicon environment
  • Strong problem-solving and analytical skills with a creative approach to debugging and resolving issues.
  • Effective communication and collaboration skills to work cohesively in a dynamic, fast-paced environment.
  • Self-motivated individual with a passion for innovation and continuous learning.


Preferred Qualifications :

  • Proven expertise in TAP (Test Access Port)
  • Prior knowledge in ASIC or FPGA design verification, particularly with x86 CPU designs.
  • Prior knowledge/background in post-silicon validation/debug is an added advantage
  • Prior experience with using fault-simulator is an added advantage

          

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location: 

Malaysia, Penang

Additional Locations:

Business group:

Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

CPU HVM Functional-Test Verification Engineer at Intel rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

  1. ●●●● Builds AI80 to 100
  2. ●●●○ Works on AI60 to 79
  3. ●●○○ Uses AI40 to 59
  4. ●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

DftVerificationDebuggingCpu ArchitecturePythonPerlSystem VerilogUVM

Questions you could be asked

  1. Tell me about a project where dft was part of your work. What did you do?
  2. Tell me about a project where verification was part of your work. What did you do?
  3. Tell me about a project where debugging was part of your work. What did you do?
  4. Tell me about a project where cpu architecture was part of your work. What did you do?
  5. Walk me through how you've used Python in your day-to-day work.

Adapt your resume

  • List these exact terms on your resume: Dft, Verification, Debugging, Cpu Architecture, and Python. An applicant tracking system matches the wording, not the idea.
  • Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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