CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG)

Intel is hiring a CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG). Level rates it ; you can apply on Intel.

Level's read on this job

Level rates this role Little AI ●○○○: aI is not part of the work.
Tools and skills the posting cites include Unix, System Verilog and mask layout.
Level classifies it as a junior role.
Level lists 805 other open roles at Intel.

AI in this role

Diploma level contract role involving mask layout design and verification of next-generation SoC/CPU products.

unixsystem-verilog

mask-layoutvlsisoc-architecturecpu-architecturesemiconductor-design

Job Details:

Job Description:

Just completed your diploma in Electrical and Electronic Engineering and ready to take the next step? Start your career with a role that gives you hands-on experience at the heart of semiconductor innovation. At Intel, you'll be immersed in real engineering challenges from day one, developing practical skills and industry knowledge that will accelerate your professional growth.

In this position, you will be involving in the training, design and development of next generation SOC/CPU for wide range of Intel products. Your responsibilities will include some of the following but not limited to:

Creates mask layouts of integrated circuits for a given specification and runs complete set of design verification tools for process design rules, electron migration, voltage drop (IR), ESD, and other reliability checks on the layouts.
Creates accurate designs that meet project needs, applying understanding of design manuals, established processes, layout elements, and basic electronic principles.
Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.
Designs and analyses floorplans, power grid, and bumps and performs all required verification on the layout blocks.
Troubleshoots a wide variety of issues up to and including layouts and tool/flow/methodology used in layout design.

Qualifications:

Who We're Looking For:
By applying to this posting, you are expressing interest in Diploma level contract job opportunities with Intel for which your qualifications relevant to the below

Diploma in Electrical and Electronic Engineering or related fields
Strong technical fundamentals and good communication skills, proficiency in English
Curious, motivated, and eager to grow in semiconductor design
Familiarity with Unix, VLSI, SoC/CPU Architecture, or System Verilog is a plus
Candidates must be open to contract-based position
Candidates must be willing to work in Penang location
Positions open only to Diploma fresh graduate

Why Start Your Early Career with Intel:

Build strong engineering foundations early in your career
Gain hands-on exposure to cutting-edge silicon design
Learn from experienced mentors and industry experts
Work in a world-class engineering environment with global collaboration
Grow in a role that offers continuous learning and professional development

Job Type:

Intel Contract Employee

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Malaysia, Kulim

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG) at Intel rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG) is an open job at Intel.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in Malaysia, Penang.
The job was posted on August 14, 2026.
Seniority: junior.
Applications are handled by Intel. Apply on Intel

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Mask LayoutVlsiSoc ArchitectureCpu ArchitectureSemiconductor DesignUnixSystem Verilog

Questions you could be asked

Tell me about a project where mask layout was part of your work. What did you do?
Tell me about a project where vlsi was part of your work. What did you do?
Tell me about a project where soc architecture was part of your work. What did you do?
Tell me about a project where cpu architecture was part of your work. What did you do?
Tell me about a project where semiconductor design was part of your work. What did you do?

Adapt your resume

List these exact terms on your resume: Mask Layout, Vlsi, Soc Architecture, Cpu Architecture, and Semiconductor Design. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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