Design Automation Engineer (TFM/EDA)

Intel is hiring a Design Automation Engineer (TFM/EDA). It pays $138k-$266k a year and Level rates it ; you can apply on Intel.

Level's read on this job

Level rates this role Little AI ●○○○: aI is not part of the work.
Level classes it as a senior role.
Intel has 793 other open roles on Level.
Posted in the last few days.

AI in this role

Job Details:

Job Description:

The Role and Impact
As an Infrastructure and DevOps Engineer at Intel Foundry, you will play a vital role in enabling and optimizing design environments that support advanced semiconductor development. You will focus on installing, maintaining, and providing technical support for design automation scripts, front-end and back-end tools, workflows, and licenses. Your contributions will help ensure seamless integration of new tools and methods, driving design processes efficiently and effectively.

Business Group
Intel Foundry is a cornerstone of Intel's mission to revolutionize semiconductor manufacturing and design. The Infrastructure and Solutions team within Intel Foundry focuses on delivering robust, scalable, and innovative solutions that empower Intel's engineering teams to achieve breakthrough results. By joining this group, you'll be contributing to Intel Foundry's goal of advancing technological innovation and supporting the design of next-generation products.

Key Responsibilities

Resolve tool/methodology issues encountered during the design path to TapeOut.
Provide training and documentation support for design ramp-up activities.
Collaborate with EDA providers to ensure required tool features meet project quality expectations.
Partner closely with PDK/library experts, flow development teams, and product design teams to drive workflow improvements.
Work with engineering compute teams to provision adequate compute capacity and troubleshoot associated issues.
Develop automation for the installation and optimization of design environments, including PDKs, EDA tools, and licenses.
Support the seamless integration of new tools and methods into existing workflows, ensuring scalability and adoption across design teams.

Qualifications:

Minimum Qualifications

US Citizenship required.
Ability to obtain a US Government Security Clearance TS/SCI.
Bachelor's degree in relevant field with 6+ years of hands-on experience in infrastructure and DevOps roles OR a Master's degree with 4+ years of experience OR a PhD with 2+ years of experience.
Experience with front-end and back-end EDA tools, flows, and methodologies, including debugging and problem-solving.
Knowledge of physical design optimization and tools flows/methodologies (TFM).
Experience with scripting languages such as Tcl, Perl, Python, and familiarity with Verilog/VHDL.
Expertise in Linux-based environments, including bash and tcsh.

Preferred Qualifications

Hands-on experience with industry-standard front-end and back-end EDA tool installations.
Experience with installing foundry PDKs and flows, including tools like Cheetah.
Experience with debugging and design automation.

Join our team and contribute to shaping the future of semiconductor innovation while growing your expertise in a dynamic, collaborative environment.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Folsom

Additional Locations:

US, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $137,610.00-265,870.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

Design Automation Engineer (TFM/EDA) at Intel rates 34 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.