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SambaNova Systems

Design Verification Engineer

SambaNova Systems is hiring a Design Verification Engineer in San Jose, United States. It pays $120k-$200k a year and Level rates it ; you can apply on SambaNova Systems.

Level's read on this job

  • Level rates this role Builds AI ●●●●: the job is building AI systems.
  • Tools and skills the posting cites include Claude, SystemVerilog and UVM.
  • Level classifies it as a mid-level role.
  • Level lists 71 other open roles at SambaNova Systems.

AI in this role

Design Verification Engineer to build UVM verification environments and validate control features for AI accelerator chips.

ClaudeSystemVerilogUVM
design-verificationdigital-designsoc-architecture

SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value.

About the team

The Design Verification team works on the RDU, SambaNova's chip for machine learning and AI workloads. This group focuses on chip-level control and initialization: sequencing, state transitions, clocking, and recovery across multiple subsystems on the chip. You'll build SystemVerilog and UVM verification environments alongside architects, RTL designers, and firmware engineers, and take ownership of verification plans from first draft through closure. The team works closely with the broader verification organization, so debugging and root-causing issues often means coordinating across groups rather than working in isolation.

About the role

SambaNova Systems is looking for a talented and motivated Design Verification Engineer, DFT to help us build state of the art RDU chips for machine learning and artificial intelligence.

Responsibilities

  • Develop and execute comprehensive verification plans for complex chip-level control and initialization features
  • Develop SystemVerilog/UVM based verification environments, test sequences, checkers, assertions, and functional coverage
  • Verify complex sequencing, dependencies, state transitions, and recovery scenarios across multiple chip subsystems
  • Develop directed and constrained-random tests to identify architectural and implementation corner cases
  • Closely work with architects, RTL designers, firmware, and other verification teams to understand design intent and drive verification closure
  • Debug simulation and regression failures and work with design teams to root-cause and resolve issues
  • Analyze regression failures, functional and code coverage and drive verification to closure

Required Qualifications

  • B.S. in Computer Science, Computer Engineering, or related field
  • 5+ years relevant industry experience
  • Strong understanding of digital design, SoC architecture, and verification methodologies
  • Strong proficiency in SystemVerilog and UVM is required
  • Experience with constrained-random verification, functional coverage, and assertion-based verification
  • Good understanding of chip initialization, control sequencing, clocking, and cross-domain interactions
  • Strong simulation debug and problem-solving skills
  • Proficiency in scripting languages, e.g. Python, Perl, TCL and shell scripting, etc. is required

Preferred Qualifications

  • Familiarity with CDC/RDC concepts and verification methodologies
  • Fluency in Claude / AI tools for verification development and debug

Base Salary Range:

Base Pay Range$120,000—$200,000 USD

Submission Guidelines
Please note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified.

EEO Policy
SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.

Benefits Summary for US-Based, Full-Time Employment Positions
SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.

How we rate this

Design Verification Engineer at SambaNova Systems rates 85 out of 100 for how much of the daily work is AI. That makes it Builds AI (AI Level 4 of 4). The level is about AI in the job, not seniority.

Classification

Builds AI. The job is building AI systems.

  1. ●●●● Builds AI80 to 100
  2. ●●●○ Works on AI60 to 79
  3. ●●○○ Uses AI40 to 59
  4. ●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Design VerificationDigital DesignSoc ArchitectureClaudeSystemVerilogUVM

Questions you could be asked

  1. Tell me about a project where design verification was part of your work. What did you do?
  2. Tell me about a project where digital design was part of your work. What did you do?
  3. Tell me about a project where soc architecture was part of your work. What did you do?
  4. What's a project where you used Claude hands-on?
  5. Walk me through how you've used SystemVerilog in your day-to-day work.

Adapt your resume

  • List these exact terms on your resume: Design Verification, Digital Design, Soc Architecture, Claude, and SystemVerilog. An applicant tracking system matches the wording, not the idea.
  • Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.
  • Lead with what you built, trained or shipped. This role is judged on the AI system itself, not the tools around it.

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