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Etched

Design Verification Engineer - Interface IP

Etched is hiring a Design Verification Engineer - Interface IP in Austin, United States. It pays $150k-$275k a year and Level rates it ; you can apply on Etched.

Level's read on this job

  • On Level's scale, this role is Builds AI ●●●●: the job is building AI systems.
  • Tools and skills the posting cites include SystemVerilog, UVM and Pcie.
  • Level classifies it as a mid-level role.
  • Level lists 114 other open roles at Etched.

AI in this role

Drive design verification for interface IP subsystems in custom hardware accelerators designed for AI inference workloads.

SystemVerilogUVMPcieEthernet
design-verificationip-subsystemshardware-verificationcoverage-closure

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.

Key responsibilities

  • End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors

  • Understand vendor IP configurations and handle handshake with internal IP team

  • Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.

  • Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.

  • Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios.

You may be a good fit if you have

  • 5+ years of design verification experience

  • You enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs.

  • You have hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches.

  • You are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.

  • You thrive in a fast-paced startup environment and can take ownership of projects with minimal direction.

  • You collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights.

Strong candidates may also have experience with

  • Experience handling vendors and integration of IP/VIP’s

  • UVM/System Verilog

Benefits

  • Medical, dental, and vision packages with generous premium coverage

    • $500 per month credit for waiving medical benefits

  • Various wellness benefits covering fitness, mental health, and more

  • Daily lunch + dinner in our office

  • Unlimited compute budget subject to ROI justification

How we’re different

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.

We greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.

How we rate this

Design Verification Engineer - Interface IP at Etched rates 85 out of 100 for how much of the daily work is AI. That makes it Builds AI (AI Level 4 of 4). The level is about AI in the job, not seniority.

Classification

Builds AI. The job is building AI systems.

  1. ●●●● Builds AI80 to 100
  2. ●●●○ Works on AI60 to 79
  3. ●●○○ Uses AI40 to 59
  4. ●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Design VerificationIp SubsystemsHardware VerificationCoverage ClosureSystemVerilogUVMPcieEthernet

Questions you could be asked

  1. Tell me about a project where design verification was part of your work. What did you do?
  2. Tell me about a project where ip subsystems was part of your work. What did you do?
  3. Tell me about a project where hardware verification was part of your work. What did you do?
  4. Tell me about a project where coverage closure was part of your work. What did you do?
  5. Walk me through how you've used SystemVerilog in your day-to-day work.

Adapt your resume

  • List these exact terms on your resume: Design Verification, Ip Subsystems, Hardware Verification, Coverage Closure, and SystemVerilog. An applicant tracking system matches the wording, not the idea.
  • Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.
  • Lead with what you built, trained or shipped. This role is judged on the AI system itself, not the tools around it.

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