Design Verification Engineer - Internal IP

Etched is hiring a Design Verification Engineer - Internal IP in Austin, United States. It pays $150k-$275k a year and Level rates it ; you can apply on Etched.

Level's read on this job

Level rates this role Builds AI ●●●●: the job is building AI systems.
Tools and skills the posting cites include SystemVerilog, UVM and Python.
Level classifies it as a senior role.
Level lists 114 other open roles at Etched.

AI in this role

Verify custom internal IP blocks for AI inference hardware accelerators focusing on UVM and SystemVerilog environments.

SystemVerilogUVMPythonPerlTcl

rtldesign-verificationasic-designcomputer-architecturedebugging

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We are seeking a Design Verification Engineer to join our Internal IP DV team. You will ensure the custom IPs powering our chips — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.

Key responsibilities

Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems).
Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks.
Debug complex datapath and protocol issues in RTL and testbench environments.
Work closely with architects and designers to validate functionality and design intent.
Partner with SW, FW, and emulation teams to ensure end-to-end bring-up and debug coverage.
Contribute to reusable DV infrastructure, coverage models, and methodology improvements.

You may be a good fit if you have

Proficiency with UVM and SystemVerilog.
Strong debugging and problem-solving skills for complex digital designs.
Solid knowledge of computer architecture and digital design fundamentals.
Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.

Strong candidates may also have experience with

Familiarity with SystemVerilog Assertions (SVA) and formal verification techniques.
Experience verifying systolic arrays, DMA engines, or NoC/AXI protocols.
Scripting skills (Python/Perl/TCL or similar) for automation, debug and regression flows.

Benefits

Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
Various wellness benefits covering fitness, mental health, and more
Daily lunch + dinner in our office
Unlimited compute budget subject to ROI justification

How we’re different

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.

We greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.

How we rate this

Design Verification Engineer - Internal IP at Etched rates 85 out of 100 for how much of the daily work is AI. That makes it Builds AI (AI Level 4 of 4). The level is about AI in the job, not seniority.

Classification

Builds AI. The job is building AI systems.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Design Verification Engineer - Internal IP is an open job at Etched.
Level rates this role AI Level 4 of 4: Builds AI.
The listed salary is $150k-$275k a year.
The role is based in Austin.
The job was posted on April 16, 2026.
Seniority: senior.
Applications are handled by Etched. Apply on Etched

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

RtlDesign VerificationAsic DesignComputer ArchitectureDebuggingSystemVerilogUVMPython

Questions you could be asked

Tell me about a project where rtl was part of your work. What did you do?
Tell me about a project where design verification was part of your work. What did you do?
Tell me about a project where asic design was part of your work. What did you do?
Tell me about a project where computer architecture was part of your work. What did you do?
Tell me about a project where debugging was part of your work. What did you do?

Adapt your resume

List these exact terms on your resume: Rtl, Design Verification, Asic Design, Computer Architecture, and Debugging. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.
Lead with what you built, trained or shipped. This role is judged on the AI system itself, not the tools around it.

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