FPGA Engineer

Cerebras is hiring an FPGA Engineer for a remote role open to applicants in United States. Level rates it ; you can apply on Cerebras.

Level's read on this job

Level rates this role Builds AI ●●●●: the job is building AI systems.
The posting lists this role as remote.
Tools and skills the posting cites include OpenAI, Rtl and FPGA.
Level classifies it as a senior role.
Level lists 121 other open roles at Cerebras.

AI in this role

Develop the full IO path and FPGA implementation for Cerebras systems that power large-scale AI training and ultra-fast inference clusters.

openairtlfpgaroce

ai-research

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services.

This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.

Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.

About The Role

The Host and Network IO Team develops the full IO path implementation between a distributed system of server nodes, through the cluster, down to the custom RoCE network stack implemented in Cerebras' system, and over the proprietary IOs onto the WSE. As an FPGA developer on the team, you will own the in-chassis IO subsystem consisting of i) several cluster-facing RoCE v2 network interfaces via a custom implementation of the RDMA protocol; ii) a large programmable switching fabric; and iii) Serial IO communication with the Cerebras WSE via a proprietary protocol. You will interface between AI application-level IO teams, cluster architecture teams, and embedded software teams to develop solutions that optimize bandwidth and latency while minimizing congestion, pauses, pause spreading, unfairness, etc. The scope of work spans multiple generations of hardware products from improvements to presently deployed hardware, implementation of upcoming systems, and design/architecting of future next-gen architectures.

Responsibilities

Lead full chassis-to-wafer IO architecture and design
Improve current RTL, implement next-gen FPGA design, define future IO architectures
Produce production-ready bitstreams for deployment into large clusters running customer inference services
Work with DV team to prevent bug slips and simplify debug
Optimize bandwidth/latency over FPGA datapath and all IO interfaces
Interface with board team facilitating and executing board bringup
Drive network performance debug of large AI clusters
Integrate leading edge networking technologies and protocols
Lead cross-functional technical projects spanning multiple teams and integrating diverse software and hardware components to deliver an improved network IO solution.
Foster clear and effective communication across teams and stakeholders.

Skills & Qualifications

5+ years industry experience generating production FPGA solutions, OR Master's/PhD in Computer or Electrical Engineering + 3 years industry experience,

Proficiency in Verilog development in Git based repo
Highly productive with FPGA placement & routing, timing closure, simulation, debug, and other FPGA tools/workflows

Network protocol familiarity (TCP, RoCE) and network debug tools such as Wireshark
Knowledge of network switch environments or willingness to learn (Arista, Juniper, etc.).
AI-augmented development environment

Why Join Cerebras

People who are serious about software make their own hardware. At Cerebras, we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we’ve reached an inflection point in our business. Members of our team tell us there are five main reasons they joined Cerebras:

Build a breakthrough AI platform beyond the constraints of the GPU.
Publish and open source their cutting-edge AI research.
Work on one of the fastest AI supercomputers in the world.
Enjoy job stability with startup vitality.
Our simple, non-corporate work culture that respects individual beliefs.

Find out more about what it's like to work at Cerebras here!

Apply today and become part of the forefront of groundbreaking advancements in AI!

Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them.

This website or its third-party tools process personal data. For more details, click here to review our CCPA disclosure notice.

How we rate this

FPGA Engineer at Cerebras rates 85 out of 100 for how much of the daily work is AI. That makes it Builds AI (AI Level 4 of 4). The level is about AI in the job, not seniority.

Classification

Builds AI. The job is building AI systems.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

FPGA Engineer is an open job at Cerebras.
Level rates this role AI Level 4 of 4: Builds AI.
The role is based in Sunnyvale, CA and is marked remote.
The job was posted on August 6, 2026.
Seniority: senior.
Applications are handled by Cerebras. Apply on Cerebras

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

AI ResearchOpenAIRtlFPGARoce

Questions you could be asked

Tell me about a research question you investigated. What did you find?
Walk me through how you've used OpenAI in your day-to-day work.
What are the limits of Rtl that you've run into, and how did you work around them?
What's a project where you used FPGA hands-on?
Walk me through how you've used Roce in your day-to-day work.

Adapt your resume

List these exact terms on your resume: AI Research, OpenAI, Rtl, FPGA, and Roce. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.
Lead with what you built, trained or shipped. This role is judged on the AI system itself, not the tools around it.

Want an expert to read your CV for this job?

Free. Send your CV and the role you want next. We reply by email within 2 to 4 business days.

Get a free CV review Get an express CV review Check your resume with the ATS resume checker

Get new remote software engineering jobs (Builds AI ●●●●) by email

One email a week with the new remote software engineering jobs (Builds AI ●●●●), each rated for how much AI is in the work. No recruiter spam, unsubscribe in one click.

Free. One email a week. Unsubscribe in one click.