IP Design Verification Engineer

Intel is hiring an IP Design Verification Engineer in Santa Clara, United States. It pays $106k-$149k a year and Level rates it ; you can apply on Intel.

Level's read on this job

On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
Tools and skills the posting cites include Claude, Copilot and Codex.
Level classifies it as a junior role.
Level lists 789 other open roles at Intel.
The role was posted within the past week.

AI in this role

Ensure quality and functionality of critical IP designs through test plans, debugging, and verification methodologies.

claudecopilotcodexverilogvhdlsystemveriloguvm

digital-designcomputer-architectureverificationdebugging

Job Details:

Job Description:

As an IP Design Verification Engineer, you will be responsible for ensuring the quality and functionality of critical IP designs through rigorous verification processes. Using industry-standard tools and methodologies, you will create and execute test plans, identify and resolve bugs, and contribute to delivering robust IP solutions. Your work will directly support the development of innovative technologies that power Intel's products and strengthen their position in the market.

Business group

The Data Center Group (DCG) focuses on developing advanced technologies that accelerate data processing and storage solutions for diverse industries. This group drives innovation in hardware and software, delivering cutting-edge products to serve growing market demands. As part of DCG, you will collaborate with teams working to redefine the capabilities of data center infrastructure, supporting Intel's mission to enable a smarter, connected world.

Key Responsibilities

Develop and implement test plans and verification strategies for IP designs using industry-standard tools and methodologies.
Identify, debug, and resolve design and verification issues to ensure robust functionality and quality.
Collaborate closely with cross-functional teams, including design, architecture, and validation teams, to identify and address potential challenges.
Generate comprehensive documentation for verification processes, test results, and design improvements.
Continuously improve verification efficiency through automation and innovative practices.

Qualifications:

This is an entry level position. You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum qualifications and are considered a plus factor in identifying top candidates. This position is not eligible for Intel immigration sponsorship

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with +1 year of hands-on experience.
+6 months of experience in:
- Hardware description languages such as Verilog or VHDL.
- Hands-on experience with verification tools like SystemVerilog, UVM, or similar environments. -
- Digital design principles and computer architecture.

Preferred Qualifications

Familiarity with scripting languages such as Python or Perl for automation purposes.
Strong analytical thinking and problem-solving skills to debug complex issues.
Familiarity with AI tools such as Claude, Copilot, Codex, etc.

Join us in driving innovation and shaping the future of data center technologies. Together, we can make a lasting impact on the world of computing.

Job Type:

College Grad

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Santa Clara

Additional Locations:

US, Massachusetts, Beaver Brook

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

IP Design Verification Engineer at Intel rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

IP Design Verification Engineer is an open job at Intel.
Level rates this role AI Level 1 of 4: Little AI.
The listed salary is $106k-$149k a year.
The role is based in US, California, Santa Clara.
The job was posted on October 22, 2026.
Seniority: junior.
Applications are handled by Intel. Apply on Intel

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Digital DesignComputer ArchitectureVerificationDebuggingClaudeCopilotCodexVerilog

Questions you could be asked

Tell me about a project where digital design was part of your work. What did you do?
Tell me about a project where computer architecture was part of your work. What did you do?
Tell me about a project where verification was part of your work. What did you do?
Tell me about a project where debugging was part of your work. What did you do?
Walk me through how you've used Claude in your day-to-day work.

Adapt your resume

List these exact terms on your resume: Digital Design, Computer Architecture, Verification, Debugging, and Claude. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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