IP Design Verification Engineer

Position Summary

Role and Responsibilities

Design & maintain UVM‑based verification environments for high‑speed serial IP blocks (e.g.,56G/112G/224G Gbps SERDES, PCIe Gen4/5, Ethernet MAC/PHY,) and security IP (AES/SHA engines, ECC, secure‑boot, root‑of‑trust).

Develop comprehensive test plans and coverage models that capture protocol corner cases, timing jitter, eye‑diagram constraints, and security threat scenarios.

Create reusable UVM components (agents, drivers, monitors, scoreboards, and protocol checkers) that can be shared across multiple serial and security projects.

Implement constrained‑random traffic generators with data‑pattern, error‑injection, and latency‑stress capabilities to validate link reliability and security robustness.

Integrate formal verification and assertion‑based checking (SVA) to capture protocol violations, key‑exchange errors, and timing violations early in the flow.

Run and maintain regression suites on industry‑standard simulators (VCS, Xcelium, Questa) and CI pipelines; monitor functional coverage, protocol coverage, and security‑feature coverage.

Collaborate closely with design, architecture, and security teams to refine specifications, resolve bugs, and drive design for testability (DfT) and low‑power considerations.

Mentor junior verification engineers, enforce coding standards, and contribute to the IPD verification methodology library.

Participate in design reviews, risk assessments, and compliance verification (e.g., PCI‑SIG, IEEE Ethernet, NIST crypto standards). 

Required Skills & Experience

System Verilog & UVM, Formal Verification expertise – 5–6 years of hands‑on verification on complex IP, with strong understanding of class‑based verification, randomization, coverage, and SVA.

High‑speed serial protocol knowledge – Practical experience verifying PCIe, Ethernet SERDES, or similar high‑throughput interfaces.

Security IP verification – Familiarity with cryptographic engines, secure‑boot flows, authentication protocols, side‑channel analysis, and related test strategies.

Simulation & automation tools – Proficient with VCS, Xcelium, or Questa; scripting in Tcl/Python for test bench generation and regression management.

Coverage‑driven verification – Ability to define functional, protocol, and security coverage models and drive them to closure.

Debugging & root‑cause analysis – Strong waveform analysis, assertion debugging, and use of log‑extraction tools to isolate failures.

Version control & CI/CD – Experience with Git and Jenkins/GitLab CI for automated regression runs.

Digital design fundamentals – Understanding of clock‑domain crossing, reset strategies, and low‑power design considerations for high‑speed blocks.

Education – B.E./B.Tech/M.Tech in Electrical/Computer Engineering or equivalent practical experience.

Skills and Qualifications

Experience – 5 to 6 Years of experience

Qualifications

• B.Tech/B.E/M.Tech/M.E

Disclaimer

Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

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