Lead RTL Design Engineer

Cerebras is hiring a Lead RTL Design Engineer in Sunnyvale, United States. It pays $200k-$299k a year and Level rates it ; you can apply on Cerebras.

Level's read on this job

Builds AI ●●●● is how Level rates this role: the job is building AI systems.
Some of the work can be done remotely, according to the posting.
The posting mentions OpenAI, Rtl and Verilog among its tools and skills.
Level classes it as a lead role.
Cerebras has 121 other open roles on Level.

AI in this role

Lead the front-end design of Cerebras Wafer Scale Engine AI chips, delivering high-performance training and inference hardware.

openairtlverilogsystemverilog

ai-researchrtl-designasic-designhardware-architecture

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services.

This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.

Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.

About The Role

As a lead front-end design engineer, you will be a key part of the world-class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE).

This role requires deep expertise in RTL design and integration, with a strong focus on delivering high-performance, power-efficient, and scalable solutions. The role also requires close collaboration and management of external ASIC vendor. You will collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of building WSE systems.

Responsibilities

Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.
Managing external ASIC vendor through product development cycle.
Work closely with PD team members for design closure to meet PPA goals.
Work closely with Design verification and DFT teams for achieving the best functional and test coverage.
Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.
Debug silicon-level functional, timing, and power issues during bring up.

Requirements

Master’s degree in Computer Science, Electrical Engineering, or equivalent.
Can work in a hybrid work environment.
8-15 years of experience in delivering complex, high performance high quality RTL designs.
Experience with Front End Chip integration and third-party IP integration.
Demonstrated experience in networking, high-performance computing, machine learning or related fields.
Proven track record of multiple silicon success.
Experience collaborating and managing external vendors.
Experience with designing/integrating high speed IO.
Networking stack experience including TCP/IP, RDMA and Ethernet.
Knowledge of PCIe, CPU interfaces and Serdes technology.
Working knowledge of scripting tools : Python, TCL.

Assets

Experience with FPGA development toolchain, including Place and Route, Floor planning and Timing Analysis is a plus.

The base salary range for this position is $200,000 to $299,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

Why Join Cerebras

People who are serious about software make their own hardware. At Cerebras, we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we’ve reached an inflection point in our business. Members of our team tell us there are five main reasons they joined Cerebras:

Build a breakthrough AI platform beyond the constraints of the GPU.
Publish and open source their cutting-edge AI research.
Work on one of the fastest AI supercomputers in the world.
Enjoy job stability with startup vitality.
Our simple, non-corporate work culture that respects individual beliefs.

Find out more about what it's like to work at Cerebras here!

Apply today and become part of the forefront of groundbreaking advancements in AI!

Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them.

This website or its third-party tools process personal data. For more details, click here to review our CCPA disclosure notice.

How we rate this

Lead RTL Design Engineer at Cerebras rates 85 out of 100 for how much of the daily work is AI. That makes it Builds AI (AI Level 4 of 4). The level is about AI in the job, not seniority.

Classification

Builds AI. The job is building AI systems.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Lead RTL Design Engineer is an open job at Cerebras.
Level rates this role AI Level 4 of 4: Builds AI.
The listed salary is $200k-$299k a year.
The role is based in Sunnyvale, CA and is marked remote.
The job was posted on August 7, 2026.
Seniority: lead.
Applications are handled by Cerebras. Apply on Cerebras

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

AI ResearchRtl DesignAsic DesignHardware ArchitectureOpenAIRtlVerilogSystemVerilog

Questions you could be asked

Tell me about a research question you investigated. What did you find?
Tell me about a project where rtl design was part of your work. What did you do?
Tell me about a project where asic design was part of your work. What did you do?
Tell me about a project where hardware architecture was part of your work. What did you do?
Walk me through how you've used OpenAI in your day-to-day work.

Adapt your resume

List these exact terms on your resume: AI Research, Rtl Design, Asic Design, Hardware Architecture, and OpenAI. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.
Lead with what you built, trained or shipped. This role is judged on the AI system itself, not the tools around it.

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