Memory Layout Design Engineer
Cisco is hiring a Memory Layout Design Engineer. Level rates it ; you can apply on Cisco.
Level's read on this job
- On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
- Tools and skills the posting cites include Cadence, Synopsys and Python.
- Level classifies it as a mid-level role.
- Level lists 1,500+ other open roles at Cisco.
AI in this role
Memory layout design engineer specializing in SRAM implementation for advanced silicon switches and routers.
This is a hybrid role with four days per week at Cisco’s Yerevan office.
Meet the Team
Our team is at the forefront of innovation, specializing in memory layout implementation for the Cisco Silicon One platform that powers the world’s most advanced switches and routers. We are a dynamic, international team dedicated to pushing the boundaries of high-performance networking technology. We offer a unique environment where technical excellence meets real-world impact. We value transparency, clear communication, and a collaborative spirit that bridges geographical divides to deliver ground breaking silicon solutions.
Your Impact
Implement high-quality memory layout implementation, specifically focusing on SRAM blocks to meet rigorous performance and reliability standards. Collaborate closely with international circuit design teams to translate schematics into robust physical designs that drive our core networking products. Perform post-layout simulations and implement necessary corrections to ensure DRC cleanliness and optimal integration with neighboring modules. Optimize layout designs for quality, visibility, and velocity to accelerate the delivery of critical silicon components.
Minimum Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 5+ years of total professional experience in physical design or layout.
- Proven experience working with industry-standard EDA tools such as Cadence or Synopsys.
- Experience with advanced node technologies such as TSMC 22nm, 12nm, 7nm, 5nm, or 2nm.
Preferred Qualifications
- 3+ years of hands-on experience specifically in SRAM layout implementation.
- Experience working within a mixed-signal or custom design environment.
- Proficiency in performing EMIR/ERC closure and providing technical support for successful tapeouts.
- Background in circuit design, including reading schematics and running simulations.
- Proficiency in scripting languages (Tcl, Python, or Perl) for design automation.
- Strong ability to communicate effectively in English, both written and spoken, to support international collaboration.
- Demonstrated ability to work both independently and within a cross-functional, multi-site team environment.
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
How we rate this
Memory Layout Design Engineer at Cisco rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.
Little AI. AI is not part of the work.
- ●●●● Builds AI80 to 100
- ●●●○ Works on AI60 to 79
- ●●○○ Uses AI40 to 59
- ●○○○ Little AI0 to 39
Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.
Prepare for this job
Built from this posting and from similar jobs on Level.
Skills and AI tools this role asks for
Questions you could be asked
- Tell me about a project where physical design was part of your work. What did you do?
- Tell me about a project where memory layout was part of your work. What did you do?
- Tell me about a project where sram was part of your work. What did you do?
- Tell me about a project where circuit design was part of your work. What did you do?
- Tell me about a project where silicon engineering was part of your work. What did you do?
Adapt your resume
- List these exact terms on your resume: Physical Design, Memory Layout, Sram, Circuit Design, and Silicon Engineering. An applicant tracking system matches the wording, not the idea.
- Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.
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