Mixed Signal Design Verification Engineer

Intel is hiring a Mixed Signal Design Verification Engineer. It pays $122k-$200k a year and Level rates it ; you can apply on Intel.

Level's read on this job

Little AI ●○○○ is how Level rates this role: aI is not part of the work.
The posting mentions System Verilog, Verilog and Vhdl among its tools and skills.
Level classes it as a mid-level role.
Intel has 826 other open roles on Level.

AI in this role

Perform functional verification and test bench development for mixed-signal logic components and silicon designs.

system-verilogverilogvhdluomovm

Job Details:

Job Description:

Intel is a global leader in technology innovation, dedicated to creating products that transform industries and improve lives worldwide. We design and manufacture advanced silicon solutions that power the digital world. Our commitment to excellence drives us to push the boundaries of technology and deliver cutting-edge solutions that meet the needs of our customers. If you are passionate about innovation and eager to contribute to transformative projects, Intel is the place for you.

Join us at Intel and be a part of a team that is shaping the future of power delivery technology.

The role’s responsibilities include but are not limited to:

Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements.
Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to mixed signal microarchitecture specifications.
Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.
Replicates, root causes, and debugs issues in the presilicon environment.
Finds and implements corrective measures to resolve failing tests.
Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
Maintains and improves existing functional verification infrastructure and methodology.

Qualifications:

You must possess the minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 3+ years of experience - OR -
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 2+ years of experience

All years of experience must be directly applied in the following technical areas:

Digital logic experience.
VHDL/Verilog/System Verilog.
Testbench component development (preferably in OVM/UVM), and design debugging skills.

Preferred Qualifications:

7+ years of related experience
Analog debug skills
Real number (current, voltage) simulation modeling and debug skills

Relevant experience can be obtained through schoolwork, classes, and project work, internships, military training and/or work experience.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Oregon, Hillsboro

Additional Locations:

US, Texas, Austin

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $122,440.00-200,340.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

Mixed Signal Design Verification Engineer at Intel rates 10 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Mixed Signal Design Verification Engineer is an open job at Intel.
Level rates this role AI Level 1 of 4: Little AI.
The listed salary is $122k-$200k a year.
The role is based in US, Oregon, Hillsboro.
The job was posted on October 6, 2026.
Seniority: mid.
Applications are handled by Intel. Apply on Intel

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

System VerilogVerilogVhdlUomOvm

Questions you could be asked

What's a project where you used System Verilog hands-on?
Walk me through how you've used Verilog in your day-to-day work.
What are the limits of Vhdl that you've run into, and how did you work around them?
What's a project where you used Uom hands-on?
Walk me through how you've used Ovm in your day-to-day work.

Adapt your resume

List these exact terms on your resume: System Verilog, Verilog, Vhdl, Uom, and Ovm. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

Want an expert to read your CV for this job?

Free. Send your CV and the role you want next. You get your review by email within 24 hours.

Get a free CV review Get your CV rewritten Check your resume with the ATS resume checker