PERC Rule Deck Development Engineer

Intel is hiring a PERC Rule Deck Development Engineer in Bengaluru, India. Level rates it ; you can apply on Intel.

Level's read on this job

Little AI ●○○○ is how Level rates this role: aI is not part of the work.
Tools and skills the posting cites include Calibre, Cadence Pegasus and Synopsys.
Level classifies it as a senior role.
Level lists 842 other open roles at Intel.

AI in this role

Develop and validate PERC rule decks for semiconductor electrical reliability verification with optional script automation.

CalibreCadence PegasusSynopsysPythonTclPerl

rule-developmentesd-verificationreliability-verificationdebuggingautomation

Job Details:

Job Description:

We are looking for a PERC Runset Development Engineer to develop and Validate PERC (Programmable Electrical Rule Checker) rule decks. The role involves working closely with PDK Team and foundry to implement PERC and ensure design compliance. Key Responsibilities: • Rule Development: Develop, validate, and maintain complex PERC rule decks to identify electrical reliability violations (e.g., ESD paths, current density, voltage stress, and floating gates). • Multi-Tool Integration: Develop and optimize verification flows across multiple EDA environments, ensuring consistency in results between Calibre PERC( preferred), Cadence Pegasus, and Synopsys tools. • Cross-Functional Collaboration: Work closely with Device Physicists, Process Integration Engineers, and Analog Designers to translate reliability requirements into programmable rules. • Debug and Analysis: Provide expert-level support to design teams in debugging PERC violations, distinguishing between true reliability risks and tool-induced false positives. • Automation: Develop scripts (Python, SKILL, Tcl, or Perl) to automate the execution, reporting, and tracking of reliability checks across different design versions. • Documentation: Maintain detailed documentation of reliability check-sets and create guidelines for designers to implement correct-by-construction layouts.

Qualifications:

Required Skills: • Experience with PERC rule development (preferably using Calibre PERC). • Knowledge of ESD, latch-up and reliability verification. • Familiarity with SVRF, TVF, Python or Tcl scripting. • Strong debugging and problem-solving skills. • Knowledge of Linux and scripting (Python/Shell/Tcl) is desirable. • Experience with advanced technology nodes is an advantage. • Team player and be able to work with global teams. Preferred Qualifications: • Bachelor's degree with 10+ years of experience, OR • Master's degree with 8+ years of experience, OR • PhD degree with 2+ years of experience in Electrical Engineering, Computer Engineering, Electronics or related field; semiconductor industry experience. • Basic AI experience is an added skill.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

PERC Rule Deck Development Engineer at Intel rates 10 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

PERC Rule Deck Development Engineer is an open job at Intel.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in India, Bangalore.
The job was posted on August 26, 2026.
Seniority: senior.
Applications are handled by Intel. Apply on Intel

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Rule DevelopmentEsd VerificationReliability VerificationDebuggingAutomationCalibreCadence PegasusSynopsys

Questions you could be asked

Tell me about a project where rule development was part of your work. What did you do?
Tell me about a project where esd verification was part of your work. What did you do?
Tell me about a project where reliability verification was part of your work. What did you do?
Tell me about a project where debugging was part of your work. What did you do?
Tell me about a project where automation was part of your work. What did you do?

Adapt your resume

List these exact terms on your resume: Rule Development, Esd Verification, Reliability Verification, Debugging, and Automation. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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