Post-Silicon Validation and Methodology Engineer
NVIDIA is hiring a Post-Silicon Validation and Methodology Engineer in Santa Clara, United States. It pays $136k-$219k a year and Level rates it ; you can apply on NVIDIA.
Level's read on this job
- Builds AI ●●●● is how Level rates this role: the job is building AI systems.
- Tools and skills the posting cites include Python, C and post silicon validation.
- Level classifies it as a senior role.
- Level lists 2,700+ other open roles at NVIDIA.
AI in this role
Senior post-silicon validation engineer building AI-assisted workflows, test infrastructure, and methodologies for next-gen silicon.
Join NVIDIA, a trailblazer at the forefront of graphics and artificial intelligence performance, efficiency, and innovation. From our roots as a groundbreaking graphic company, we have evolved into a global leader in artificial intelligence, continuously pushing the boundaries to tackle complex challenges across diverse industries.
The problems that break late in a silicon program almost always break here first — at the boundary where architecture, design, firmware, and silicon meet reality in the lab. NVIDIA's Silicon Co-Design Group has an end-to-end view that almost no team anywhere can claim: from early architecture through bring-up to product release, across GPU, SoC, and CPU programs spanning Datacenter, Gaming, Robotics, Automotive, and Embedded. We are looking for a hardware engineer who builds the methods, test infrastructure, and coverage strategies that find issues before software is production-ready — and who rewires the team's workflow when the old approach isn't fast enough.
What you will be doing:
Own bring-up, validation, qualification, tuning, and productization plans for next-generation silicon — from first power-on through PVT sign-off.
Partner across architecture, build, firmware, and software teams to define requirements for power management and clocking features, then drive coverage from pre-silicon through production.
Build and deploy AI assisted lab workflows. These workflows automate bring-up telemetry and silicon measurement data evaluation. They provide anomaly detection on regression results and debug-triage tooling. This tooling reduces the time from observation to root-cause hypothesis. The team runs these tools during every bring-up, not as occasional scripts.
Build the test infrastructure, characterization methodologies, and bring-up playbooks that shift post-silicon coverage left and raise velocity across programs.
Lead root-cause analysis on the hardest HW/SW interaction issues — with the measurement field, instrumentation judgment, and hypothesis rigor to close them under schedule pressure.
Identify where current processes break and redesign them: bring-up sequencing, debug forums, regression frameworks, and the lab metrics that tell us whether we are actually improving.
What we need to see:
BS or MS in Electrical or Computer Engineering (or equivalent experience), plus 5+ years in silicon bring-up, validation, debug, or productization.
Deep fundamentals across digital development, microarchitecture, timing, clocking, power, noise, and control systems — and the ability to reason across the HW/SW boundary under real lab constraints.
Hands-on lab proficiency: oscilloscopes, logic analyzers, power analyzers, and the instinct to know which instrument answers which question during a bring-up.
Strong programming and scripting proficiency: Python, C/C++; experience building lab automation or test infrastructure that other specialists adopt and depend on — not just personal scripts.
Proficiency in the use of AI tools to accelerate silicon validation work — automated analysis of bring-up logs, regression data, or lab instrumentation output; anomaly detection on silicon measurement datasets; or LLM-assisted debug triage. We want to understand what you built, how you validated its trustworthiness, and where you decided the measurement had to stay manual.
Ways to stand out from the crowd:
Hardware proof of crafting: debug infrastructure you built in the lab, characterization methodologies adopted across programs, build DFT feature specs or in-system test suites you developed, or margin test flows that caught issues before production.
Proficiency in bring-up experience with GPU/SoC architecture
Experience crafting or scaling in-system test and DFT features for production silicon, with familiarity with fault models, DPPM, and RAS.
Build concrete examples of redesigning how a team debugs in the lab — faster triage, smarter hypothesis trees, automated measurement reporting — and the resulting increase in bring-up velocity or quality.
Our team is at the forefront of innovation in silicon co-design, contributing to the development of groundbreaking technologies. We offer a dynamic work environment where your contributions will directly impact the company's success. Join us to advance your career in a role where you can truly make a difference. With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers.
Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD.You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until October 17, 2026.This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.How we rate this
Post-Silicon Validation and Methodology Engineer at NVIDIA rates 85 out of 100 for how much of the daily work is AI. That makes it Builds AI (AI Level 4 of 4). The level is about AI in the job, not seniority.
Builds AI. The job is building AI systems.
- ●●●● Builds AI80 to 100
- ●●●○ Works on AI60 to 79
- ●●○○ Uses AI40 to 59
- ●○○○ Little AI0 to 39
Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.
Prepare for this job
Built from this posting and from similar jobs on Level.
Skills and AI tools this role asks for
Questions you could be asked
- Tell me about a project where post silicon validation was part of your work. What did you do?
- Tell me about a project where hardware debug was part of your work. What did you do?
- Tell me about a project where silicon bring up was part of your work. What did you do?
- Tell me about a project where test infrastructure was part of your work. What did you do?
- Tell me about a project where automation was part of your work. What did you do?
Adapt your resume
- List these exact terms on your resume: Post Silicon Validation, Hardware Debug, Silicon Bring Up, Test Infrastructure, and Automation. An applicant tracking system matches the wording, not the idea.
- Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.
- Lead with what you built, trained or shipped. This role is judged on the AI system itself, not the tools around it.
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