Power Delivery Design Engineer

Intel is hiring a Power Delivery Design Engineer in Toronto, Canada. Level rates it ; you can apply on Intel.

Level's read on this job

Builds AI ●●●● is how Level rates this role: the job is building AI systems.
Tools and skills the posting cites include Simulation Tools, Pcb Design Tools and power delivery design.
Level classifies it as a senior role.
Level lists 787 other open roles at Intel.
The role was posted within the past week.

AI in this role

Designs power delivery networks and hardware solutions specifically for next-generation AI accelerators and GPUs.

simulation-toolspcb-design-tools

power-delivery-designpower-integrityhardware-designpcb-layout

Job Details:

Job Description:

Are you passionate about computing and AI accelerators?

Do you thrive on innovation and want to disrupt the industry? Are you eager to work with leading AI hardware engineers on Intel's latest architecture? If you love collaborating with diverse teams to create best-in-class AI compute platforms, Intel's GPE department has exciting opportunities for you.

As a member of the GPE team, you will develop hardware and platform solutions for Intel products, including the newest IPs targeted at next-generation GPUs and AI accelerators.

You will have the opportunity to engage in enabling technologies in PCB design, manufacturing, testing, and debugging. We are a winning team with a clear vision of delivering competitive and cutting-edge products, and we are committed to building the best products and developing the best skills for our team.

Key Responsibilities:

Work on end-to-end power delivery design and development, from initial concept to implementation of power delivery requirements and ecosystem enabling power integrated circuits.
Own power integrity simulation for the platform power delivery network: build and correlate VRM-to-die PDN models, run DC IR-drop and AC target-impedance analysis, and perform transient droop and Ldi/dt studies across die, package, and PCB to set the decoupling and stack up strategy before layout is committed.
Apply knowledge of power conversion topologies, including components, compensation circuits/stability analysis, drop/droop analysis, simulation tools, and techniques, as well as PCB layout and design tools, to characterize performance and validate correlation of simulation modeling and results.
Design and validate platform power conversion and management solutions, including energy management, and perform simulation and optimization for package and PCB, including stack up, power/ground noise plane assignment, decoupling solutions, and/or power sequencing requirements.
Design for debug: architect observability into the board from the start, including per-rail voltage and current sense points, Kelvin-sense and probe landing points, telemetry and current-monitor access (SVID/PMBus/IMON), rail-level isolation and enable control, and voltage-margining , so power-on and post-silicon issues can be isolated on the first board instead of a respin.
Design for flexibility: build configurability into the power delivery solution so a single board can support multiple SKUs and derivatives, using stuffing options for phase count and decoupling, pin-compatible dual-source regulator footprints, rail split/merge and current headroom for higher-power SKUs, and programmable load line, compensation, and VID range.
Create and execute test plans to validate and characterize power delivery solutions.
Correlate bench and VR test tool measurements with simulation results to improve simulation model accuracy and close the loop on power integrity assumptions.
Conduct failure analysis and root cause investigations for power delivery issues, implementing corrective actions to prevent recurrence.
Collaborate with silicon and platform architects to generate solutions and analyses, delivering content into platform design guides as solution collaterals for end customers.
Collaborate with cross-functional teams, including board design, SW/FW, and systems validation, to ensure seamless integration of power delivery solutions.

Qualifications:

Minimum Qualifications, you must possess the below minimum qualifications to be initially considered for this position.

Bachelor's or Master's degree in Electrical Engineering or a related field.
5+ years of experience in:

- Designing low voltage, high current, multi-phase DC-DC switching regulators (buck, boost, etc.) to meet stringent targets, optimizing the design for transient response and conversion efficiency.
- Working with signal/power integrity and power delivery network simulation tools such as Cadence Sigrity PowerDC/PowerSI, Ansys SIwave etc. to develop accurate models of circuit design
- Design and optimize accurate power delivery simulation models using SPICE and time-based simulation tools (LTSpice, SIMPLIS etc.) based on SOC design power requirements.
- Power delivery network modeling across die, package, and PCB, including stackup, plane assignment, decoupling network design, and S-parameter extraction and correlation.
- Experience using oscilloscopes and DAQ for hardware troubleshooting and debugging.
- Interacting with Signal Integrity, Layout, and Mechanical engineers, with working knowledge of SI/PI, PCB layout, and mechanical aspects of board designs.

Preferred Qualifications, are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Experience designing for debug and testability on power delivery hardware, including sense and telemetry instrumentation, voltage margining, and rail isolation for post-silicon bring-up.
Experience designing configurable power delivery solutions that support multiple SKUs and derivative products from a single board design.
Identify new technologies/interfaces and develop board power delivery architecture.
Experience in project management, including leading projects and manage timelines and resources effectively.
Familiarity with emerging technologies such as GaN power devices, switched capacitor topology, etc.
Experience delivering products for high-volume production and cost optimization.
Knowledge of board and power management (HW/SW/FW) debugging.
Willing to provide hardware technical support to ODM/OEM board vendors.
Willingness to travel globally to meet internal teams and external customers.

Job Type:

Experienced Hire

Shift:

Shift 1 (Canada)

Primary Location:

Canada, Toronto

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Annual Salary Range for jobs which could be performed in Canada

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Canada Accommodation:

Intel is committed to a culture of accessibility. Intel provides accommodations to applicants and employees with disabilities. Find information and request accommodation here.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

Power Delivery Design Engineer at Intel rates 80 out of 100 for how much of the daily work is AI. That makes it Builds AI (AI Level 4 of 4). The level is about AI in the job, not seniority.

Classification

Builds AI. The job is building AI systems.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Power Delivery Design Engineer is an open job at Intel.
Level rates this role AI Level 4 of 4: Builds AI.
The role is based in Canada, Toronto.
The job was posted on October 20, 2026.
Seniority: senior.
Applications are handled by Intel. Apply on Intel

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Power Delivery DesignPower IntegrityHardware DesignPcb LayoutSimulation ToolsPcb Design Tools

Questions you could be asked

Tell me about a project where power delivery design was part of your work. What did you do?
Tell me about a project where power integrity was part of your work. What did you do?
Tell me about a project where hardware design was part of your work. What did you do?
Tell me about a project where pcb layout was part of your work. What did you do?
Walk me through how you've used Simulation Tools in your day-to-day work.

Adapt your resume

List these exact terms on your resume: Power Delivery Design, Power Integrity, Hardware Design, Pcb Layout, and Simulation Tools. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.
Lead with what you built, trained or shipped. This role is judged on the AI system itself, not the tools around it.

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