Semiconductor Device Modeling Engineer

Intel is hiring a Semiconductor Device Modeling Engineer. It pays $174k-$330k a year and Level rates it ; you can apply on Intel.

Level's read on this job

Little AI ●○○○ is how Level rates this role: aI is not part of the work.
Tools and skills the posting cites include Python, Hspice and Spectre.
Level classifies it as a senior role.
Level lists 798 other open roles at Intel.
The role was posted within the past week.

AI in this role

Develop advanced semiconductor compact device models and simulation flows for Intel's technology nodes.

pythonhspicespectreiccapmbp

compact-modelingdevice-modelingfinfetgaafetbsim-cmg

Job Details:

Job Description:

About the team and organization

Compact Device Modeling Group (CDMG) is part of Intel's Design Technology Platform (DTP) organization. DTP is a key pillar in enabling Intel to deliver design, development and manufacturing services that allow Intel Foundry customers to deliver winning products to the marketplace. Your work will directly enable design teams to get to the market faster with leadership products based on innovative technologies.

As a member of CDMG you will be at the forefront of co-optimizing Intel's state-of-the-art process technology which allows customers with diverse design needs to enable best-in-class products for data-centric applications. As a semiconductor device modeling engineer, you will be playing a key role to support compact modeling activities for Intel's new technologies.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

Master's degree in Electrical Engineering or a related discipline and at least 5+ years of industry experience in the semiconductor field; or Ph.D. in Electrical Engineering or a related discipline with a minimum of 3+ years of industry experience in the semiconductor field.
3+ years of hands-on experience with BSIM-CMG and other compact models for transistor modeling at advanced nodes (e.g., FinFET, GAA).
Proficiency with extraction tools (e.g., ICCAP, MBP) and commercial simulators such as HSPICE, Spectre, etc.
Strong background in IV/CV fitting, model retargeting, and corner/statistical variation modeling.
Experience developing LLE models for FinFET or GAAFET technologies.
Skilled in Python scripting for automation and documentation.

Preferred Qualifications

Ph.D. in Electrical Engineering or a related discipline with 8+ years of industry experience in the semiconductor field.
Deep expertise in compact modeling, including one or more of the following areas:
- Layout-dependent effects (LDE) and their impact on circuit performance.
- Modeling using Open Model Interface (OMI)
- Strong understanding of process flow, layout, and basic circuit design/simulation.
- Modeling self-heating effects and their influence on device and circuit performance.
- Development of methodologies for device targeting (e.g., transistors) and benchmarking circuits (e.g., ring oscillators), including corners and statistical variation models.
- o Demonstrated experience in technical leadership and Proven capability to collaborate across multiple teams and geographies.
- Experience with machine learning algorithms and their application is data analysis and compact model development.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Oregon, Hillsboro

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $173,660.00-330,340.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

Semiconductor Device Modeling Engineer at Intel rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Semiconductor Device Modeling Engineer is an open job at Intel.
Level rates this role AI Level 1 of 4: Little AI.
The listed salary is $174k-$330k a year.
The role is based in US, Oregon, Hillsboro.
The job was posted on October 30, 2026.
Seniority: senior.
Applications are handled by Intel. Apply on Intel

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Compact ModelingDevice ModelingFinfetGaafetBsim CmgPythonHspiceSpectre

Questions you could be asked

Tell me about a project where compact modeling was part of your work. What did you do?
Tell me about a project where device modeling was part of your work. What did you do?
Tell me about a project where finfet was part of your work. What did you do?
Tell me about a project where gaafet was part of your work. What did you do?
Tell me about a project where bsim cmg was part of your work. What did you do?

Adapt your resume

List these exact terms on your resume: Compact Modeling, Device Modeling, Finfet, Gaafet, and Bsim Cmg. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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