Senior ASIC Design Engineer - Memory Subsystem

NVIDIA is hiring a Senior ASIC Design Engineer - Memory Subsystem in Santa Clara, United States. It pays $136k-$219k a year and Level rates it ; you can apply on NVIDIA.

Level's read on this job

On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
The posting mentions Verilog, Vhdl and Perl among its tools and skills.
Level classes it as a senior role.
NVIDIA has 2,600+ other open roles on Level.

AI in this role

Design and micro-architect complex memory subsystem ASIC components and interconnects for GPUs.

verilogvhdlperl

asic-designrtlmemory-subsystemhardware

Today, NVIDIA is tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. Come join the team and see how we can make a lasting impact on the world.

NVIDIA is looking for an Senior ASIC Design Engineer to join our Memory Subsystem Team!

What you'll be doing:

As a member of our Memory Subsystem Design team, you will collaborate with architects/design verification/formal verification/physical design team to deliver a world-class solution. NVIDIA SOC Interconnects, ordering controllers and memory accelerators are among the industry's most sophisticated because of the complex area, latency, power, bandwidth and quality-of-service requirements.
In this position, you will have the opportunity to be responsible for the micro-architecture and design including RTL design, synthesis and timing analysis using innovative CAD tools and using the latest process technologies.

What we need to see:

BS or MS in Electrical Engineering or Computer Engineer or related degree (or equivalent experience)
5+ years of experience
Experience with high-speed coherent interconnects, protocol bridges, hardware-managed coherency and system level caches is a plus
Experience with multiple clock domains and asynchronous interfaces is a plus
Knowledge of industry specifications like CHI/CXL/PCI-E is a plus.
Strong proficiency of Verilog or VHDL.
Scripting language like PERL

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you!

Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:
136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until November 3, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

How we rate this

Senior ASIC Design Engineer - Memory Subsystem at NVIDIA rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Senior ASIC Design Engineer - Memory Subsystem is an open job at NVIDIA.
Level rates this role AI Level 1 of 4: Little AI.
The listed salary is $136k-$219k a year.
The role is based in US, CA, Santa Clara.
The job was posted on October 13, 2026.
Seniority: senior.
Applications are handled by NVIDIA. Apply on NVIDIA

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Asic DesignRtlMemory SubsystemHardwareVerilogVhdlPerl

Questions you could be asked

Tell me about a project where asic design was part of your work. What did you do?
Tell me about a project where rtl was part of your work. What did you do?
Tell me about a project where memory subsystem was part of your work. What did you do?
Tell me about a project where hardware was part of your work. What did you do?
Walk me through how you've used Verilog in your day-to-day work.

Adapt your resume

List these exact terms on your resume: Asic Design, Rtl, Memory Subsystem, Hardware, and Verilog. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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