Senior Cache Coherency Architect

NVIDIA is hiring a Senior Cache Coherency Architect in Santa Clara, United States. It pays $152k-$242k a year and Level rates it ; you can apply on NVIDIA.

Level's read on this job

On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
Level classes it as a senior role.
NVIDIA has 2,700+ other open roles on Level.

AI in this role

We are seeking an experienced Senior Cache Coherency Architect to join our ambitious team at NVIDIA. This opportunity allows you to be part of a world-class organization that develops scalable, low-latency, high-bandwidth coherent interconnect systems. These systems power groundbreaking NVIDIA products such as Grace-CPU-Superchip, Grace-Hopper-Superchip, and Vera-Rubin.

In this role, you will contribute to the architecture of cache-coherent interconnect and cache subsystems, including architecture definition, modeling, and implementation. You will collaborate with CPU, GPU, memory subsystem, and SoC architects to define coherency solutions that integrate effectively into SoC designs. The role requires close partnership with multiple IP creation and verification teams throughout the project lifecycle. This position provides the chance to create a meaningful impact across product lines ranging from consumer graphics to automotive and AI platforms.

What you’ll be doing:

Define consistent interconnect architecture, cache-coherency protocols, and high-performance on-chip interconnect interfaces.
Contribute to interconnect IP block specifications, build, verification, and integration into the NoC fabric to ensure cache-coherency compliance.
Collaborate with architects to guarantee the interconnect architecture aligns with project power, performance, and area (PPA) requirements.
Develop and maintain functional and performance models for the NoC fabric and IP units to assist with analysis and validation.
Collaborate with cross-functional design and verification teams (simulation, emulation, and formal) to ensure implementations align with architectural specifications.
Support silicon bring-up and post-silicon debug as needed.

What we need to see:

Master’s degree in electrical engineering, Computer Engineering, Computer Science, or equivalent experience.
5+ years of experience in processor design or other high-performance semiconductor designs.
Deep understanding of cache coherency, with hands-on experience in industry-standard protocols (e.g., AXI, ACE, CHI).
Experience authoring specifications and designing cache-coherent interconnects.
Strong understanding of system and memory subsystem architecture, with a focus on cache-coherent interconnect.
Experience developing coherent IP models (e.g., VIPs, BFMs) for simulation and emulation.
Proficiency in C, C++, Python, and Verilog.

Join us and help build the future of computing at NVIDIA!

Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:
152,000 USD – 241,500 USD for Level 3; and 184,000 USD – 287,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until November 3, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

How we rate this

Senior Cache Coherency Architect at NVIDIA rates 24 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.