IntelSenior CAD Engineer – Physical Design Signoff
Intel is hiring a Senior CAD Engineer – Physical Design Signoff in Bengaluru, India. Level rates it ; you can apply on Intel.
Level's read on this job
- Level rates this role Little AI ●○○○: aI is not part of the work.
- The posting mentions Python, Tcl and physical design among its tools and skills.
- Level classes it as a senior role.
- Intel has 789 other open roles on Level.
- Posted within the past two weeks.
AI in this role
Senior CAD engineer developing physical design signoff automation with a minor exposure to ML and agentic AI methods.
Job Description:
We are looking for a highly motivated Senior Physical Design Signoff Automation Engineer to develop and deploy signoff methodologies and automation solutions for advanced CPU and SoC designs. The candidate will work closely with Physical Design, Timing, Power, Reliability, and CAD teams to improve signoff quality, productivity, and turnaround time. The ideal candidate possesses deep expertise in Parasitic Extraction, Static Timing Analysis (STA), Electrical Rule Checking (ERC), and Power Integrity signoff, along with strong programming and automation skills. Key Responsibilities Develop and enhance automation solutions for Physical Design signoff flows, including: RC Extraction Static Timing Analysis (STA) Electrical Rule Checking (ERC) Power Integrity (IR Drop/EM) Signal Integrity (SI) Create scalable automation frameworks to reduce signoff turnaround time and improve engineering productivity. Develop scripts and tools to automate signoff checks, debugging, reporting, and data analysis. Analyze and resolve timing, extraction, ERC, and power signoff issues in collaboration with design teams. Drive methodology improvements to improve signoff convergence, quality, and correlation across implementation stages. Partner with EDA vendors and internal CAD teams to evaluate and deploy new signoff capabilities. Build dashboards and reporting infrastructure to monitor signoff health and project readiness.Qualifications:
Minimum Qualifications M.Tech/M.S. in Electrical Engineering, VLSI, Computer Engineering, or related field. 8+ years of industry experience in Physical Design, Signoff, CAD, or Design Automation. Strong proficiency in: Python Tcl Shell scripting Preferred Qualifications Experience working on advanced process technologies (3nm, 2nm, Intel 18A/14A, or equivalent). Understanding of AOCV/POCV and variation-aware timing methodologies. Familiarity with power delivery networks, EM analysis, and reliability signoff. Experience in Machine-learning methods and Agentic AI systems to solve CAD problems Exposure to CPU core, high-performance compute, or large SoC designs. Experience with distributed computing environments and large-scale signoff infrastructure.
Job Type:
Experienced HireShift:
Shift 1 (India)Primary Location:
India, BangaloreAdditional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust
N/AWork Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.How we rate this
Senior CAD Engineer – Physical Design Signoff at Intel rates 20 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.
Little AI. AI is not part of the work.
- ●●●● Builds AI80 to 100
- ●●●○ Works on AI60 to 79
- ●●○○ Uses AI40 to 59
- ●○○○ Little AI0 to 39
Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.
Prepare for this job
Built from this posting and from similar jobs on Level.
Skills and AI tools this role asks for
Questions you could be asked
- Tell me about a project where physical design was part of your work. What did you do?
- Tell me about a project where static timing analysis was part of your work. What did you do?
- Tell me about a project where automation was part of your work. What did you do?
- Tell me about a project where vlsi was part of your work. What did you do?
- Walk me through how you've used Python in your day-to-day work.
Adapt your resume
- List these exact terms on your resume: Physical Design, Static Timing Analysis, Automation, Vlsi, and Python. An applicant tracking system matches the wording, not the idea.
- Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.
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