Senior Circuit Design Engineer - Noise

NVIDIA is hiring a Senior Circuit Design Engineer - Noise in Santa Clara, United States. It pays $168k-$265k a year and Level rates it ; you can apply on NVIDIA.

Level's read on this job

Level rates this role Little AI ●○○○: aI is not part of the work.
Level classifies it as a senior role.
Level lists 2,700+ other open roles at NVIDIA.

AI in this role

We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in improving the netlist and timing quality of our designs and if you are a self-starter and highly motivated individual who loves to collaborate and find solutions to hard technical problems, join us today!

For over two decades, NVIDIA has been at the forefront of transforming how the world computes—from pioneering the GPU in 1999 to powering today's AI revolution. We're a company that thrives on collective innovation, where diverse perspectives drive breakthrough solutions in Graphics, Data Center, and Artificial Intelligence. As both a learning machine and organization, we believe the best ideas emerge when brilliant minds from all backgrounds collaborate to solve the world's most complex challenges. Join us in building technology that amplifies human potential and creates opportunities for everyone to thrive in the digital future.

What you’ll be doing:

Participate in cutting edge Processor design in deep submicron technologies.
Work as part of a global circuits team to design innovative circuits (digital, semi-custom and mixed-signal analog) for silicon correlation and noise mitigation.
Collaborate and work closely with cross-functional teams to improve the performance, and reliability of NVIDIA's next generation products by performing detailed transistor-level analysis on the design.
Drive the design and physical implementation of digital and/or mixed-signal analog circuit IPs for voltage and noise sensing using custom and automated tools.
Create prototypes of patentable ideas on test chips and drive them to be deployed across the entire line of products.
Be a mentor/technical lead for junior team members.

What we need to see:

BSEE (or equivalent experience);MS preferred in Electrical or Computer Engineering with 8+ years of experience
Good understanding of deep submicron process issues and digital circuit design techniques
Familiarity/experience with analog and mixed-signal block design such as op-amp, comparator, ADC etc.
Hands on experience running Spice simulations, EM/IR analysis, and static timing analysis/closure
Experience with spice simulation for noise analysis, loop stability analysis, ac/dc/transient analysis, monte-carlo, etc

Ways to stand out from the crowd:

Hands on experience in design and analysis of digital and mixed-signal voltage sensors is a plus
Exposure to flash ADC design is a plus
Experience with RTL, logic synthesis and verification, knowledge of Place and Route, and understanding of Design-for-test (DFT) is a plus.
Proficiency in scripting language, such as, Perl, Tcl, Make and automation methods/algorithms is a plus.
Prior leadership experience is a plus.

#LI-Hybrid

Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary range for this position is 168,000 USD – 264,500 USD.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until November 3, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

How we rate this

Senior Circuit Design Engineer - Noise at NVIDIA rates 17 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.