Senior Design Verification Engineer

Intel is hiring a Senior Design Verification Engineer in Santa Clara, United States. It pays $164k-$312k a year and Level rates it ; you can apply on Intel.

Level's read on this job

On Level's scale, this role is Uses AI ●●○○: an ordinary role that requires AI tools.
Tools and skills the posting cites include AI Assisted Tools, CAD and Rtl.
Level classifies it as a senior role.
Level lists 842 other open roles at Intel.

AI in this role

Senior Design Verification Engineer to own end-to-end verification of critical chassis and interconnect IP blocks using AI-assisted workflows.

AI Assisted ToolsCADRtl

design-verificationrtlprotocol-verificationformal-verificationml-driven-verification

Job Details:

Job Description:

About the Role
Intel is seeking a Senior Design Verification Engineer for the Silicon Chassis team. In this role, you will own end-to-end verification of critical chassis and interconnect IP blocks from planning through signoff. You will drive quality in testbench architecture, test plan and coverage closure while working closely with architecture, design, and software teams. This position requires strong technical depth in DV methodologies, protocol verification, and memory subsystem behavior, with enough breadth in RTL, physical design, and CAD to contribute across traditional discipline boundaries. AI-assisted workflows are part of everyday development here. Consistent execution against schedule and quality goals is expected.

Responsibilities will include but are not limited to:

Own verification planning and execution for key IP features across IP and subsystem integration points
Build scalable verification environments and targeted test plans with reusable test benches, checkers, VIPs, and behavioral models
Collaborate closely with architecture, design, and software teams from specification through bringup; contribute across role boundaries when needed to unblock progress and maintain execution quality
Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics
Lead IP delivery to multiple customers while ensuring technical excellence; balance competing requirements, schedules, and resources across teams
Drive convergence of simulation and formal verification into unified bug hunting and coverage closure strategies; evaluate and adopt emerging methodologies including ML-driven verification flows
Mentor and develop verification engineers; establish verification best practices and raise team-level execution quality
Comfortable using AI-assisted development tools as part of everyday workflow; track record of delivering reusable, configurable verification collateral

Core Competencies

Excellent communication and organizational skills with a track record of delivering high-quality silicon on schedule; able to adapt as tools, methodologies, and role definitions evolve

Qualifications:

The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

Bachelor of Science Degree in Electrical or Computer Engineering, Computer Science, or in a STEM related field
10+ years of experience in design verification (DV); with extensive background in IP DV, and subsystem and SoC-level verification
Experience in interconnects, caches, and memory subsystems, including multiple bus protocols such as AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL; cache coherency and memory consistency models
Experience in verification of global functions including debug, trace, clock and power management, RAS, QoS, and security feature
Experience in simulation and formal verification methodologies including UVM, SVA, ABV, and co-simulation; proficiency in low-power verification techniques, HDL/verification languages, and industry-standard EDA tools
Hands-on coding experience across SystemVerilog/UVM, C/C++, Python, and build systems
Experience working with RTL, physical design, and CAD tool flows; contribute outside core DV responsibilities as needed.

Preferred Experience

Post graduate degree in Electrical or Computer Engineering, Computer Science, or in a STEM related field
Experience with formal verification tools (JasperGold, VC Formal, or similar) and emulation or FPGA-based verification; track record of combining formal and simulation for unified bug closure
Prior work with system IPs such as MMUs (SMMU or IOMMU) and interrupt controllers, and working knowledge of the associated software stacks

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Santa Clara

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

Senior Design Verification Engineer at Intel rates 45 out of 100 for how much of the daily work is AI. That makes it Uses AI (AI Level 2 of 4). The level is about AI in the job, not seniority.

Classification

Uses AI. An ordinary role that requires AI tools.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Senior Design Verification Engineer is an open job at Intel.
Level rates this role AI Level 2 of 4: Uses AI.
The listed salary is $164k-$312k a year.
The role is based in US, California, Santa Clara.
The job was posted on July 16, 2026.
Seniority: senior.
Applications are handled by Intel. Apply on Intel

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Design VerificationRtlProtocol VerificationFormal VerificationML Driven VerificationAI Assisted ToolsCAD

Questions you could be asked

Tell me about a project where design verification was part of your work. What did you do?
Tell me about a project where rtl was part of your work. What did you do?
Tell me about a project where protocol verification was part of your work. What did you do?
Tell me about a project where formal verification was part of your work. What did you do?
Tell me about a project where ml driven verification was part of your work. What did you do?

Adapt your resume

List these exact terms on your resume: Design Verification, Rtl, Protocol Verification, Formal Verification, and ML Driven Verification. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.
Put the AI tool in a bullet point about what you did, not just in a skills list. This role treats it as a required part of the job.

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