IntelSenior EDA Tools Hardware Engineer
Intel is hiring a Senior EDA Tools Hardware Engineer in Santa Clara, United States. It pays $142k-$269k a year and Level rates it ; you can apply on Intel.
Level's read on this job
- Level rates this role Little AI ●○○○: aI is not part of the work.
- Tools and skills the posting cites include Synopsys Nanotime, Cadence Liberate and Spice.
- Level classifies it as a senior role.
- Level lists 798 other open roles at Intel.
AI in this role
Senior hardware engineer developing EDA tool flows and transistor-level timing characterization for custom silicon IPs.
Job Description:
The Role and Impact
Join Intel's mission to engineer world-changing technology as a Senior EDA Tools Hardware Engineer. We are seeking an experienced EDA CAD / Tool Flow Development Engineer to develop and maintain transistor-level timing characterization flows for custom IPs, embedded memories, SRAMs, register files, and compiler-generated macros across advanced semiconductor technologies.
This role focuses on characterization methodology, CAD infrastructure, automation, and model validation for complex custom macros and memory IPs. The engineer will work closely with custom circuit, memory design, STA, and methodology teams to enable scalable and silicon-accurate timing, power, and noise modeling flows.
The ideal candidate has strong expertise in SPICE-based characterization, Liberty model generation, custom macro timing behavior, and large-scale automation using industry-standard tools such as Synopsys NanoTime and Cadence Liberate.
Key Responsibilities
- Develop, test, and analyze engineering design automation tools, flows, and methodologies to improve efficiency and optimize power and performance.
- Collaborate with EDA vendors to define, evaluate, and test next-generation design tools and flows.
- Create and verify unique hardware designs, integrating components into hierarchical systems to support end-to-end EDA tool testing for advanced technology nodes.
- Define and enable methodologies for hardware development related to EDA tools and technology node advancements.
- Support and enhance platforms, databases, scripts, and tools used for design automation.
- Provide digital design, verification, full-chip integration, physical layout, power, performance, clocking, and timing for future TFM development
Qualifications:
The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
- Degree in one of the following options:
- Option 1: Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or in a related field, with 6+ years of relevant experience.
- Option 2: Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or in a related field with 4+ years of relevant experience.
- Option 3: Ph.D. in Computer Engineering, Electrical Engineering, Computer Science, or in a related field with 2+ years of relevant experience.
- 3+ years of experience with Timing characterization methodologies in one of the following: (i.e. Nanotime, Liberate, or PrimeLib).
- Experience with Liberty timing models.
Preferred Qualifications
- Experience in any of the following:
- SPICE simulation
- CMOS circuits
- Memory architecture fundamentals
- STA fundamentals
- Advanced-node custom IP or memory characterization flows
- Scripting and automation skills in Linux environments
Take the next step in your career by joining Intel and becoming a part of our mission to shape the future of technology. Apply today to make an impact with your expertise.
Job Type:
Experienced HireShift:
Shift 1 (United States of America)Primary Location:
US, California, Santa ClaraAdditional Locations:
US, California, Folsom, US, Oregon, Hillsboro, US, Texas, AustinPosting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust
N/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.How we rate this
Senior EDA Tools Hardware Engineer at Intel rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.
Little AI. AI is not part of the work.
- ●●●● Builds AI80 to 100
- ●●●○ Works on AI60 to 79
- ●●○○ Uses AI40 to 59
- ●○○○ Little AI0 to 39
Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.
Prepare for this job
Built from this posting and from similar jobs on Level.
Skills and AI tools this role asks for
Questions you could be asked
- Tell me about a project where eda was part of your work. What did you do?
- Tell me about a project where hardware design was part of your work. What did you do?
- Tell me about a project where timing characterization was part of your work. What did you do?
- Tell me about a project where signal integrity was part of your work. What did you do?
- Walk me through how you've used Synopsys Nanotime in your day-to-day work.
Adapt your resume
- List these exact terms on your resume: Eda, Hardware Design, Timing Characterization, Signal Integrity, and Synopsys Nanotime. An applicant tracking system matches the wording, not the idea.
- Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.
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