Senior Mixed Signal Circuit Design Engineer

NVIDIA is hiring a Senior Mixed Signal Circuit Design Engineer in Santa Clara, United States. It pays $168k-$265k a year and Level rates it ; you can apply on NVIDIA.

Level's read on this job

Little AI ●○○○ is how Level rates this role: aI is not part of the work.
Level classes it as a senior role.
NVIDIA has 2,600+ other open roles on Level.

AI in this role

We are now looking for a Senior Mixed Signal Design Engineer to be part of the Mixed Signal design team building next generation NVLINK. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. The team is responsible for the development and implementation of high-speed interfaces and analog circuits. Gain hands-on experience taking innovative integrated circuit designs at data rates of 100Gbps and higher from concept through silicon characterization. Come join our dynamic team today!

What you'll be doing:

You will be part of the design and implementation of high-speed interface circuits; Have the chance to create projects including high speed transceivers and high frequency PLLs.
Become involved in the design, simulation, and verification of mixed-signal circuits; Lead mask designers, provide mentorship for floorplan and layout design.
Provide support to the lab characterization of silicon and pursue the challenges of circuit design in deep submicron CMOS.
You will take designs through implementation and productizing.
Collaborate with multi-functional teams.

What we need to see:

MS in Electrical Engineering (or equivalent experience), PhD preferred
4+ years of design experience in CMOS analog / mixed-signal circuit
Working knowledge of Cadence custom design tools, circuit simulator, timing analysis tool; Your extensive design experience in Data Converters, Tx, Rx, CDR, PLL for high-speed IO interfaces.
Someone who's an exceptional teammate with good interpersonal skills; Validated experience in leading and mentoring designers.
In-depth understanding of deep submicron CMOS process and related circuit design issues; Proven experience in silicon bring-up, debugging and use of lab instrumentation is required.
Knowledge in system level timing budget, signal integrity, and power integrity is a plus; Experience in Verilog, Matlab, Nanotime is helpful.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us.

Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:
168,000 USD – 264,500 USD for Level 4; and 196,000 USD – 310,500 USD for Level 5.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until November 3, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

How we rate this

Senior Mixed Signal Circuit Design Engineer at NVIDIA rates 28 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.