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SambaNova Systems

Senior RTL Design Engineer

SambaNova Systems is hiring a Senior RTL Design Engineer in Austin and San Jose, United States. It pays $120k-$200k a year and Level rates it ; you can apply on SambaNova Systems.

Level's read on this job

  • Builds AI ●●●● is how Level rates this role: the job is building AI systems.
  • Tools and skills the posting cites include SystemVerilog, Git and Python.
  • Level classifies it as a senior role.
  • Level lists 72 other open roles at SambaNova Systems.

AI in this role

Design component units of Reconfigurable Dataflow Unit ASICs for SambaNova's AI acceleration systems.

SystemVerilogGitPythonLinuxAxiPcieEthernetHbmDdr
asic-designrtl-designcomputer-architecturedigital-logic-designmicroarchitecture

SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value.

About the team

The RTL design team builds the compute datapath, on-chip network, and memory subsystems inside SambaNova's RDU AI accelerator. Their work spans microarchitecture through tape-out: RTL implementation, PPA trade-offs, quality gates like lint, CDC, and LEC, and timing closure with

About the role

SambaNova RTL Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs behind our AI acceleration systems. You'll own blocks within a larger subsystem, contributing sections of the microarchitecture specification, writing and debugging the RTL, and carrying your blocks through implementation, tape-out, and silicon bring-up. You'll work alongside principal engineers, architects, design verification, and physical design, and take on larger blocks as you build depth in our architecture

Required Qualifications

  • B.S. in Electrical Engineering, Computer Engineering, or Computer Science
  • 5+ years of experience in ASIC RTL design
  • Solid foundation in computer architecture and digital logic design
  • Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs
  • Experience making design decisions that trade off power, performance, and area
  • Knowledge of industry-standard interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR
  • Experience with digital logic synthesis tools and static timing analysis
  • Proficiency with industry-standard tools for linting, clock domain crossing, and logical equivalence checking
  • Experience implementing SystemVerilog Assertions to check design intent
  • Familiarity with tools and simulators for hardware performance analysis and tuning
  • Familiarity with Git for managing release cycles
  • Scripting skills in Python and Linux shell

Preferred Qualifications

  • M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
  • Exposure to a full ASIC development cycle through tape-out and production silicon
  • Interest in or knowledge of AI workload acceleration techniques
  • Experience with low-power design techniques such as clock gating and DVFS at advanced process nodes
  • Exposure to emulation or FPGA prototyping platforms for pre-silicon validation

Base Salary Range:

Base Pay Range$120,000—$200,000 USD

Submission Guidelines
Please note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified.

EEO Policy
SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.

Benefits Summary for US-Based, Full-Time Employment Positions
SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.

How we rate this

Senior RTL Design Engineer at SambaNova Systems rates 85 out of 100 for how much of the daily work is AI. That makes it Builds AI (AI Level 4 of 4). The level is about AI in the job, not seniority.

Classification

Builds AI. The job is building AI systems.

  1. ●●●● Builds AI80 to 100
  2. ●●●○ Works on AI60 to 79
  3. ●●○○ Uses AI40 to 59
  4. ●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Asic DesignRtl DesignComputer ArchitectureDigital Logic DesignMicroarchitectureSystemVerilogGitPython

Questions you could be asked

  1. Tell me about a project where asic design was part of your work. What did you do?
  2. Tell me about a project where rtl design was part of your work. What did you do?
  3. Tell me about a project where computer architecture was part of your work. What did you do?
  4. Tell me about a project where digital logic design was part of your work. What did you do?
  5. Tell me about a project where microarchitecture was part of your work. What did you do?

Adapt your resume

  • List these exact terms on your resume: Asic Design, Rtl Design, Computer Architecture, Digital Logic Design, and Microarchitecture. An applicant tracking system matches the wording, not the idea.
  • Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.
  • Lead with what you built, trained or shipped. This role is judged on the AI system itself, not the tools around it.

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