Senior Standard Cell Library Engineer

Intel is hiring a Senior Standard Cell Library Engineer in Santa Clara, United States. It pays $122k-$232k a year and Level rates it ; you can apply on Intel.

Level's read on this job

On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
Tools and skills the posting cites include Cadence Virtuoso, Synopsys Custom Compiler and Cadence Liberate.
Level classifies it as a senior role.
Level lists 864 other open roles at Intel.

AI in this role

Design, characterize, and validate standard cell libraries and physical design flows for Intel's foundry.

Cadence VirtuosoSynopsys Custom CompilerCadence LiberateSynopsys Fusion Compiler

standard-cell-layoutasic-designcircuit-designtiming-optimization

Job Details:

Job Description:

About the Organization
Intel's Foundry Standard Cell team is seeking a talented and motivated Senior Design Engineer to join our growing team. In this role, you will design leading edge experiments to develop, characterize, and test standard cells. You will play a critical role in enabling customers by listening to their needs and building the solutions.

Key Responsibilities

Defines, implements, characterizes, and validates design solutions to meet design requirements for power, performance, area (PPA), manufacturability, and cost.
Capable of implementing all aspects of the physical design flow, including standard cell circuit, layout, extraction, characterization, and optimization of timing, congestion, power, signal integrity, and reliability to achieve goals.
Collaborates closely with all standard cell collateral to understand design requirements and develop robust implementation and validation strategies.
Reviews and validates work to ensure compliance with design, manufacturing, and quality requirements.
Fast turn-around experiments - devising experiments, running them end to end, and guiding data driven decisions across multiple audiences (peer working groups, management, and technical leaders).
Run end-to-end flows to generate, validate, and release custom standard cell collateral per on demand requests.

Core Competencies

Strong written and verbal communication skills are required with the ability to tailor the communication based on the audience.

Qualifications:

The Minimum qualifications listed below are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor's degree in: Electrical Engineering, Electronics Engineering, Nanoscience, Microelectronics, Computer Engineering, or a STEM related field.
2+ years' experience in one or more of the following:
- Standard cell layout
- Standard cell abstract modeling
- Standard cell characterization
- ASIC design and verification
Experience using one or more of the following tools: Cadence Virtuoso, Synopsys Custom Compiler, Cadence Abstract Generator, Synopsys PrimeLib, Cadence Liberate, Synopsys Fusion Compiler, Cadence Innovus, Cadence Tempus, Synopsys PrimeTime, Synopsys HSpice, Synopsys StarRC, Synopsys ICV, Cadence Pegasus, Siemens Calibre.

Preferred Qualifications:

Post Graduate Degree in: Electrical Engineering, Electronics Engineering, Nanoscience, Microelectronics, Computer Engineering, or a STEM related field.
Unix proficiency and basic software skills using command line languages (csh, bash, perl, python) are highly valued.

We are looking for innovative thinkers ready to make an impact in the evolving semiconductor landscape. Apply today and be part of Intel's mission to create technologies that connect and enrich lives globally.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Santa Clara

Additional Locations:

US, California, Folsom

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

Senior Standard Cell Library Engineer at Intel rates 1 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Senior Standard Cell Library Engineer is an open job at Intel.
Level rates this role AI Level 1 of 4: Little AI.
The listed salary is $122k-$232k a year.
The role is based in US, California, Santa Clara.
The job was posted on September 1, 2026.
Seniority: senior.
Applications are handled by Intel. Apply on Intel

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Standard Cell LayoutAsic DesignCircuit DesignTiming OptimizationCadence VirtuosoSynopsys Custom CompilerCadence LiberateSynopsys Fusion Compiler

Questions you could be asked

Tell me about a project where standard cell layout was part of your work. What did you do?
Tell me about a project where asic design was part of your work. What did you do?
Tell me about a project where circuit design was part of your work. What did you do?
Tell me about a project where timing optimization was part of your work. What did you do?
Walk me through how you've used Cadence Virtuoso in your day-to-day work.

Adapt your resume

List these exact terms on your resume: Standard Cell Layout, Asic Design, Circuit Design, Timing Optimization, and Cadence Virtuoso. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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