SOC Design Verification Engineer

Samsung Electronics is hiring an SOC Design Verification Engineer in Bengaluru, India. Level rates it ; you can apply on Samsung Electronics.

Level's read on this job

Little AI ●○○○ is how Level rates this role: aI is not part of the work.
Level classifies it as a senior role.
Level lists 592 other open roles at Samsung Electronics.

AI in this role

Position Summary

About Samsung Semiconductor India Research (SSIR)

With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.

As one of the largest R&D centres outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.

Role and Responsibilities

Will be involved in SOC verification and responsible for verifying one or more IP(s)/Block(s) from test plan development to GLS sign-off with code/functional coverage closure. He/she will work closely work with cross-domains team (PD, RTL, DFT) for reviews, debug and for technical discussions.

Required Skills:

• 4~7 years working experience in Sub-system, SOC level verification (including GLS).
• Experience in developing test bench from scratch -- UVM components : BFM, agents, monitor, scoreboard, checkers et al and 3rd party VIP integration.
• Proficient in coding Pre-Silicon functional verifications tests to verify design to meet spec. requirements.
• Creates efficient test plans for RTL validation and Gate level simulations.
• Expertise in System Verilog, UVM, and/or OVM based verification methodologies.
• Experience in OOPs concepts, coverage driven constrained random validation.
• Must have very good knowledge on AMBA standards (AXI, AHB, APB).
• Looking for individual with Hands-on experience in Memory protocols such as - HBM2/HBM3 OR LPDDR4~5x OR GDDRx is highly desirable.
• Any experience on high-speed protocols like - PCIe, Ethernet, High speed SerDes is a plus
• Working knowledge of scripting, SVA.
• Execution of DV test plan which includes
      • Creation/modification of the test bench.
      • Implementation of software/programming sequence.
      • Creation/integration of checkers and scoreboards from unit level UVM environment.
      • Resolution of compile and simulation errors.
      • Innovative optimizations to reduce simulation time.
      • Complex failure debug: Isolating design related failure by systematically identifying and eliminating issues related to
          Test bench/programming sequence in close collaboration with unit verification engineers, logic designers and architects
• Coverage sign-off - Code (block, expression, fsm), toggle and functional coverage
• Continuous regressions (X-prop, Power-aware and performance runs ) and failure closure

Skills and Qualifications

Experience – 4 to 7 years

Qualifications

B.Tech/B.E/M.Tech/M.E

Disclaimer

Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

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How we rate this

SOC Design Verification Engineer at Samsung Electronics rates 24 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.