Sr SOC Emulation Validation Engineer

Intel is hiring a Sr SOC Emulation Validation Engineer. Level rates it ; you can apply on Intel.

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Level rates this role Little AI ●○○○: aI is not part of the work.
Level classifies it as a mid-level role.
Level lists 864 other open roles at Intel.
The role was posted in the last few days.

AI in this role

Job Details:

Job Description:

The Role and Impact As a SoC Design Verification Engineer at Intel, you will be responsible for performing functional logic verification of integrated System-on-Chip (SoC) designs to ensure they meet specifications and are ready for production. You will develop scalable and reusable verification plans, test benches, and environments, and play a key role in identifying and resolving issues to ensure the highest quality designs. Your work will directly contribute to delivering cutting-edge technology for Intel's next-generation Client CPU SoC solutions. Business Group You will be part of Intel's Design Engineering Group (DEG), which is focused on designing and verifying high-performance, power-efficient computing solutions. The team supports Intel's mission to shape the future of technology by driving innovation across the Semiconductor industry. Joining this group means becoming part of a collaborative environment that fosters creativity and continuous improvement while contributing to Intel's broader goals in hyper-scale computing and innovation. Key Responsibilities - Define and develop scalable and reusable block, subsystem, and SoC verification plans, test benches, and verification environments. - Execute verification plans, including emulation and system simulation models, to verify designs and analyze power/performance while identifying and debugging potential issues. - Collaborate closely with SoC architects, microarchitects, RTL developers, postsilicon, and physical design teams to ensure the functionality and performance of complex architectural features. - Perform root cause analysis and debug issues in the presilicon environment, implementing corrective actions to resolve failing tests. - Incorporate security measures into verification test plans, including regression and debug testing to ensure comprehensive coverage. - Maintain and continuously improve existing functional verification infrastructure and methodologies. - Absorb learning from postsilicon validation and update verification test plans to address missing coverage areas for future products.

Qualifications:

Minimum Qualifications - Bachelor's or BS degree in Electronics, Electrical Engineering, Computer Engineering, Computer Science, or a related field. - 3+ years of hands-on experience in digital design verification with a Bachelor's degree, 2+ years of experience with a Master's degree, or 0 years of experience with a PhD. - Proficiency in programming languages and scripting such as Python, Perl, C++, and UNIX environments. - Knowledge of Industry Architecture (IA) and Register Transfer Level (RTL) design concepts. Preferred Qualifications - Demonstrated ability to work collaboratively with design teams and architects to ensure chip functionality. - Experience developing innovative validation strategies incorporating machine learning (ML) and artificial intelligence (AI) techniques to improve efficiency and quality. - Strong problem-solving skills, with a track record of debugging complex issues at both the block and system levels. - Familiarity with emulation models, system simulation, and automated testing methodologies. If you are ready to work on cutting-edge technology in a collaborative and innovative environment, we encourage you to join us in shaping the next generation of computing solutions.

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Malaysia, Kulim

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

Sr SOC Emulation Validation Engineer at Intel rates 27 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.