Level

NVIDIA

SRAM Design Engineer

NVIDIA is hiring an SRAM Design Engineer in Santa Clara, United States. It pays $116k-$190k a year and Level rates it ; you can apply on Level.

AI in this role

Design embedded SRAM and develop automated SRAM compilers while leveraging AI tools for daily circuit design tasks.

claudeclaude-codecodexcadence-virtuoso
sram-designcircuit-designcompiler-developmentsilicon-validation

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.The Digital IP (DIP) group at NVIDIA develops IP for every chip designed at NVIDIA. This group works closely with internal SOC design, silicon testing, and productization teams that turn our IP into products that change the world. One of the roles fulfilled by the DIP group is to develop sophisticated SRAM compilers that are used extensively by our SOC design partners. We are looking to hire a skilled and creative SRAM circuit designer to help achieve these goals in a high-visibility position.


What you'll be doing:

  • Embedded SRAM design: Transistor-level circuit design, supervising layout implementation, physical and logical verification, and debug of SRAM macros.
  • SRAM compiler development: Envisioning, defining, and coding more efficient ways to automate the simultaneous assembly and validation of multiple unique SRAM macros using NVIDIA's extensive compute resources.
  • Advanced development: Exploring the potential of future process nodes and developing techniques to realize optimal power, performance, and area characteristics.
  • Guiding SOC design, silicon test, and productization efforts: Collaborate with SOC design partners to help them achieve their overall performance and cost goals, guide the silicon test and characterization efforts, and working with productization teams to prepare new silicon for the demanding requirements of real-world applications.

What we need to see:

  • BSEE minimum (or equivalent experience), MSEE or PhD
  • 2+ years of professional experience in SRAM design
  • Familiarity with Cadence Virtuoso schematic and layout capture tools
  • Willingness and ability to use AI effectively in day-to-day tasks

Ways to stand out from the crowd

  • Self-motivation, attention to detail, and good written, verbal, and presentation skills are essential to success in this role
  • We rely heavily on AI coding and analysis tools such as Codex and Claude Code. The more developed your skills in this area, the better
  • Silicon testing and debugging experience

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until October 19, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

How we rate this

SRAM Design Engineer at NVIDIA rates 45 out of 100 for how much of the daily work is AI. That makes it Uses AI (AI Level 2 of 4). The level is about AI in the job, not seniority.

Classification

Uses AI. An ordinary role that requires AI tools.

  1. ●●●● Builds AI80 to 100
  2. ●●●○ Works on AI60 to 79
  3. ●●○○ Uses AI40 to 59
  4. ●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Open the description and count.

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Sram DesignCircuit DesignCompiler DevelopmentSilicon ValidationClaudeClaude CodeCodexCadence Virtuoso

Questions you could be asked

  1. Tell me about a project where sram design was part of your work. What did you do?
  2. Tell me about a project where circuit design was part of your work. What did you do?
  3. Tell me about a project where compiler development was part of your work. What did you do?
  4. Tell me about a project where silicon validation was part of your work. What did you do?
  5. Walk me through how you've used Claude in your day-to-day work.

Adapt your resume

  • List these exact terms on your resume: Sram Design, Circuit Design, Compiler Development, Silicon Validation, and Claude. An applicant tracking system matches the wording, not the idea.
  • Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.
  • Put the AI tool in a bullet point about what you did, not just in a skills list. This role treats it as a required part of the job.

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