STA Synthesis Engineer

Position Summary

Role and Responsibilities

Roles and Responsibilities

·         Complete ownership of timing constraint at image sensor full chip and sub system levels. This includes:

o    Timing constraint (Hierarchical, Flat) development and release for Synthesis/PD work

o    Timing constraint validation using various EDA tools

o    Analysis of pre-layout and post-layout timing reports and debug

o    Incremental update of constraint as and when it is required

o    Working with RTL,  DFT and PD teams independently and driving in timing closure both at sub system and full  chip level.

·         RTL PPA analysis (physical and power aware) at sub system levels for power, performance, area trade-off. This includes:

o    Running relevant EDA tool and generate reports

o    Analysing the reports

o    Working with RTL , PD teams to improve the quality of RTL and Physical implementation

·         Development of necessary scripts in TCL, Perl and/or Python for efficiency improvement

Required Skill Set:

·         Strong understanding in STA fundamentals, AOCV/POCV, signal integrity, cross-talk noise, process variation, timing ECO generation etc.

·         Hands-on experience in writing timing constraints at full chip and/or sub system level

·         Hands on experience in timing constraint validation and clean up at full chip and/or sub system level

·         Hands-on experience in pre and post layout timing analysis (both flat and hierarchical) and debug

·         Experience in driving timing convergence at full chip and/or sub system level.

·         Hands-on experience with STA tools: PrimeTime and/or Tempus

·         Experience in both physical and UPF aware synthesis using Industry standard EDA tools

·         Good understanding of UPF basics, different power optimization techniques

·         Experience in UPF based static low power check (RTL, Netlist) at full chip and/or sub system level is a plus

·         Experience in power analysis at full chip and/or sub system level is a plus

·         Knowledge of ASIC Back End flows and relevant Tools

·         Good automation skill using  TCL, Python and/or Perl

·         Ability to handle multiple project execution

·         Ability to work with multiple stakeholders independently

·         Good analytical and problem solving skills

Experience – 4 to 7 Years of Experience

Qualifications

• B.Tech/B.E/M.Tech/M.E

Skills and Qualifications

Disclaimer

Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

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