Staff EMIB-T Substrate Yield Engineer

Intel is hiring a Staff EMIB-T Substrate Yield Engineer in Tokyo, Japan. Level rates it ; you can apply on Intel.

Level's read on this job

On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
The posting mentions computer vision among its tools and skills.
Level classes it as a lead role.
Intel has 877 other open roles on Level.
Posted in the last few days.

AI in this role

computer-vision

Job Details:

Job Description:

Intel's APTM organization is seeking a highly driven Staff Technology Development Substrate Yield Engineer to drive supplier yield, defect reduction, technical issue closure, and process-control maturity supporting next-generation EMIB-T substrates across Japan suppliers. The team will be chartered to lead yield performance for next-generation advanced packaging technologies, including EMIB-T (Embedded Multi-die Interconnect Bridge with TSV), Intel's most advanced platform for heterogeneous integration partnering with substrate suppliers locally at the HVM factories. This is a high-visibility, high-accountability role with significant responsibility for enabling successful technology development and manufacturing readiness across both Intel Foundry Services (IFS) and Intel Product Groups (IPG). The ideal candidate is a self-starter who thrives in ambiguous and fast-paced environments, proactively drives issues to closure, and requires minimal supervision. Success in this role requires strong technical depth, urgency in execution, the ability to influence cross-functional teams and suppliers, and a relentless focus on delivering yield and program milestones. Key responsibilities Own day-to-day yield performance and issue closure for assigned supplier lines, modules, products, or process areas. Lead structured investigations from containment and hypothesis development through experiments, failure analysis, corrective action, and sustainment. Use statistical and spatial analytics to identify signatures by line, tool, material, panel position, geometry, product, and time. Establish clear supplier actions, owners, completion criteria, control limits, and verification plans. Support DFM/DFY, qualification, ramp readiness, change control, and deployment of dashboards or automated analytics. Capture reusable learning and communicate facts, hypotheses, decisions, and residual risks clearly.

Qualifications:

Minimum qualifications Masters degree with 4+years or PhD with 2+years in Engineering, Materials Science, Physics, Chemistry, Data Science, or a related technical discipline. 4+ years of experience in semiconductor manufacturing, advanced packaging, substrate technology, yield engineering, process engineering, or a closely related field. Hands-on experience in substrate, advanced packaging, or semiconductor yield engineering, including statistical analysis, defect reduction, process optimization, SPC, DFM/DFY, defect metrology, failure analysis, and HVM execution. Strong analytical and problem-solving skills with the ability to make data-driven decisions in complex environments. Experience working across multiple organizations and influencing stakeholders to achieve results. Demonstrated ability to independently manage complex technical issues, execute with urgency, and drive actions to closure. Experience developing or deploying yield monitoring systems, automated analytics, dashboards, image analytics, computer vision, AI/ML-based defect detection, or automated defect classification systems. Professional proficiency in Japanese and English sufficient for technical work, subject to HR validation. Preferred qualifications Experience working directly with substrate suppliers and external manufacturing partners. Demonstrated program leadership experience, including coordinating cross-functional technical teams and driving execution in high-visibility, high-impact environments. Experience with semi-additive processing, build-up films, microvias, copper plating, lithography, lamination, embedded silicon, TSV, 2.5D/3D packaging, or heterogeneous integration. Prior experience supporting technology development, qualification, and manufacturing ramp of advanced semiconductor technologies. Experience with automated data pipelines, dashboards, image analytics, computer vision, AI/ML defect detection, or automated defect classification.

Job Type:

Experienced Hire

Shift:

Shift 1 (Japan)

Primary Location:

Japan, Tokyo

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

Staff EMIB-T Substrate Yield Engineer at Intel rates 25 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.