ASIC Design Verification Engineer

What You'll Do

It used to be that high-speed packet forwarding was performed in dedicated ASIC designs. These days we are looking to make those ASICs more general and programmable. Cisco Common ASIC Group is looking for an expert Senior Verification Engineer to drive existing projects and engage in new development of our next generation switching systems.

As part of ASIC team, you will be developing the ASICs at the heart of each of these switch products. There are only a very few teams worldwide that implement such devices. Every time you access the Internet, chances are, your data's been through one of our switches.

Who You'll Work With

You will work with Cisco’s best-in-class switching solution team. Our team is responsible for driving integration of the Nexus systems and ACI with software, including OpenStack, Docker, and Open vSwitch, to help our customers build multitenant clouds.

Who You Are

You are a talented, motivated ASIC verification engineer to join the team and contribute to the verification of very complex ASICs. You will have a Design Verification background, hands-on experience in System Verilog and UVM methodology, with in-depth knowledge of C++, scripting, as well as ASIC design and verification flow.

You’ll be part of Cisco Common ASIC Group, focusing on developing various test benches and contributing to different aspects of verification infrastructure.

You will collaborate closely with the design team and the hardware team to verify the ASIC in simulation, in emulation and during ASIC bring up.

Responsibilities Include:

• Designing UVM/SystemVerilog testbenches.
• Defining new DV methodologies.
• Enhancing existing testbenches.
• End-to-end verification of various design blocks.
• Contributing to top level verification.
• Be a part of emulation testing efforts.
• Participate in the ASIC bring-up

Education and Experience Required:

• Bachelor’s or master’s degree in EE and CE.
• 5+ years of ASIC Design Verification

Knowledge and Skills:

• Hands-on and deep understanding of System Verilog and UVM methodology
• Ability to construct testbench including scoreboard, agents, sequencers, and monitors
• Ability to debug issues independently
• Proven Scripting experience (Python, Perl, TCL, shell programming) is a plus
• Proficient in functional coverage and constrained random DV environments
• Proficient in merging and analyzing code coverage data generated functional simulation
• Good written and verbal communication skills
• Very good hands-on knowledge on latest high speed Ethernet protocol and packets
• Good working knowledge in C, C++ programming and debugging skills
• Collaborative and team-focused, with the drive to learn and grow

We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you.