ASIC Design Verification Engineer | UVM | Exp. 8+ years
AI in this role
- You will contribute to developing Cisco’s progressive data center solutions by crafting industry-leading sophisticated chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include
- Architect block, cluster and top-level DV environment infrastructure.
- Develop DV infrastructure from scratch.
- Maintain and improve existing DV environments.
- Develop test plans and tests for qualifying design at block, cluster and higher-level environments with mix of constraint random and advised stimulus.
- Ensure complete verification coverage through implementation and review of code and functional coverage.
- Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist.
- Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and efficient performance.
- Support testing of design in emulation.
- Lead all aspects of and manage the ASIC bring-up process.
- Bachelor’s Degree or equivalent experience in EE, CE, or other related field.
- 7+ years of related ASIC design verification experience.
- Proficient in ASIC verification using UVM/System Verilog.
- Proficient in verifying sophisticated blocks, clusters and top level for ASIC.
- Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.
- Scripting experience with Perl and/or Python.
- Master’s Degree in EE or CE with 5+ years of relevant work experience.
- Experience with Forwarding logic/Parsers/P4.
- Experience with Veloce/Palladium/Zebu/HAPS.
- Formal verification (iev/vc formal) knowledge.
- Demonstrated ability on one or more protocols (PCIe, Ethernet, RDMA, TCP).
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
How we score this
ASIC Design Verification Engineer | UVM | Exp. 8+ years at Cisco scores 31 out of 100 on AI centrality, which makes it AI Level 1 of 4 (Little AI) on this board. The level measures how much of the work is AI, not seniority.
AI Level 1. The work itself involves no AI, or AI only appears as scenery, such as a company tagline.
- AI Level 480 to 100
- AI Level 360 to 79
- AI Level 240 to 59
- AI Level 10 to 39
Bands come from how often the tools, models and workflows of the role are named in the posting itself. Open the description and count.
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